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From:   Inochi Amaoto <inochiama@outlook.com>
To:     Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>,
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        Adrian Hunter <adrian.hunter@intel.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Nikita Shubin <n.shubin@yadro.com>,
        Inochi Amaoto <inochiama@outlook.com>
Cc:     linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
        linux-riscv@lists.infradead.org
Subject: Re: [PATCH V3] perf vendor events riscv: add T-HEAD C9xx JSON file
Date:   Sat, 24 Jun 2023 14:42:27 +0800
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> Hello,
>
> On Fri, Jun 23, 2023 at 6:33 PM Inochi Amaoto <inochiama@outlook.com> wrote:
> >
> > Hi, Namhyung
> >
> > Since there is a fault in T-HEAD documentation, I am not sure whether
> > the perf events are correct. As a result, I suggest temporarily suppressing
> > this patch until I extract the correct events from its vendor perf driver.
> > I will prepare a new V4 patch once it is finished.
>
> Sure, thanks for letting me know.
>
> >
> > As for c9xx wildcard, the T-HEAD provides a `MCPUID` vendor CSR to allow
> > its CKLINK to get the detail CPU info. The format of this CSR are:
> >
> > ------------------------------------------------
> > |31   28|27  26|25    22|21   18|17    8|7    0|
> > | index | WLRL | family | class | model | WLRL |
> > ------------------------------------------------
> >
> > And for C9xx series (only index 0000 is vaild for us, as `MCPUID` also
> > provides other index).
> >
> > | 0000 | xx | 0100 | class | xxxxxxxxxx | xxxxxxxx |
> >
> > The class codes are:
> >
> > C910: 0011
> > c906: 0100
> >
> > The CSR is a M-mode only CSR, so now I'm exploring a clean way to
> > integrate this CSR into the kernel. Any advice?
>
> I don't know about the details.  Is this CSR available from user space?
> If not, you could add it somewhere in the sysfs.
>
> Thanks,
> Namhyung
>
>

This CSR is not directly available from user space, I will try sysfs. Thanks.

> >> Hello,
> >>
> >> On Thu, May 18, 2023 at 2:50 AM Inochi Amaoto <inochiama@outlook.com> wrote:
> >>>
> >>>> licheerv # perf record
> >>>> [  432.015618] watchdog: BUG: soft lockup - CPU#0 stuck for 26s!
> >>>> [perf:117]
> >>>> [  460.015617] watchdog: BUG: soft lockup - CPU#0 stuck for 52s!
> >>>> [perf:117]
> >>>> [  488.015616] watchdog: BUG: soft lockup - CPU#0 stuck for 78s!
> >>>> [perf:117]
> >>>> [  516.015617] watchdog: BUG: soft lockup - CPU#0 stuck for 104s!
> >>>> [perf:117]
> >>>>
> >>>> But that's not related to your patch anyway.
> >>>
> >>> Same issue on c920, but it did not always occur.
> >>> Like a sbi issue for T-HEAD cpus.
> >>>
> >>>> I am strongly against using "c9xx" wildcard, i would prefer declaring
> >>>> them separate (especially taking in mind that c920 is c910 with vector
> >>>> - AFAIK), but that's up to Arnaldo to decide.
> >>>
> >>> AFAIK, there is no reliable way to distinguish c906 and c910 cores. And
> >>> the events of c910 and c920 are the same (according to the draft document
> >>> of the c920).
> >>>
> >>> Anyway, I agree to let Arnaldo decide.
> >>>
> >>>> Tested-by: Nikita Shubin <n.shubin@yadro.com>
> >>
> >> I'm collecting patches on behalf of Arnaldo this time.
> >> It seems this patch was not picked up for a long time.
> >>
> >> I think we can make changes for the c9xx wildcard later
> >> if needed.  I'll process it in the current form.
> >>
> >> Thanks,
> >> Namhyung
> >>
>