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[83.9.30.197]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b004f85858e52dsm254280lfi.138.2023.06.24.05.18.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 24 Jun 2023 05:18:38 -0700 (PDT) Message-ID: Date: Sat, 24 Jun 2023 14:18:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH V5 3/5] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 Content-Language: en-US To: Jagadeesh Kona , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Bjorn Andersson , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Satya Priya Kakitapalli , Imran Shaik , Ajit Pandey References: <20230623164619.11464-1-quic_jkona@quicinc.com> <20230623164619.11464-4-quic_jkona@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230623164619.11464-4-quic_jkona@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.06.2023 18:46, Jagadeesh Kona wrote: > Add support for the camera clock controller for camera clients to be > able to request for camcc clocks on SM8550 platform. > > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Signed-off-by: Jagadeesh Kona > --- Reviewed-by: Konrad Dybcio Konrad > Changes since v4: > - Removed overloading .l config with CAL_L and RINGOSC_CAL_L fields > - Used clk_lucid_ole_pll_configure() to configure lucid ole pll's > - Used module_platform_driver() instead of subsys_initcall() > Changes since v3: > - No changes > Changes since v2: > - No changes > Changes since v1: > - Sorted the PLL names in proper order > - Updated all PLL configurations to lower case hex > - Reused evo ops instead of adding new ops for ole pll > - Moved few clocks to separate patch to fix patch too long error > > drivers/clk/qcom/Kconfig | 7 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/camcc-sm8550.c | 3383 +++++++++++++++++++++++++++++++ > 3 files changed, 3391 insertions(+) > create mode 100644 drivers/clk/qcom/camcc-sm8550.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 263e55d75e3f..2e9a3c050a6e 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -765,6 +765,13 @@ config SM_CAMCC_8450 > Support for the camera clock controller on SM8450 devices. > Say Y if you want to support camera devices and camera functionality. > > +config SM_CAMCC_8550 > + tristate "SM8550 Camera Clock Controller" > + select SM_GCC_8550 > + help > + Support for the camera clock controller on SM8550 devices. > + Say Y if you want to support camera devices and camera functionality. > + > config SM_DISPCC_6115 > tristate "SM6115 Display Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index e6e294274c35..6d8810a4896f 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -102,6 +102,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o > obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o > obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o > obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o > +obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o > obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o > obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o > obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o > diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c > new file mode 100644 > index 000000000000..075bea32087c > --- /dev/null > +++ b/drivers/clk/qcom/camcc-sm8550.c > @@ -0,0 +1,3383 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "common.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + DT_IFACE, > + DT_BI_TCXO, > +}; > + > +enum { > + P_BI_TCXO, > + P_CAM_CC_PLL0_OUT_EVEN, > + P_CAM_CC_PLL0_OUT_MAIN, > + P_CAM_CC_PLL0_OUT_ODD, > + P_CAM_CC_PLL1_OUT_EVEN, > + P_CAM_CC_PLL2_OUT_EVEN, > + P_CAM_CC_PLL2_OUT_MAIN, > + P_CAM_CC_PLL3_OUT_EVEN, > + P_CAM_CC_PLL4_OUT_EVEN, > + P_CAM_CC_PLL5_OUT_EVEN, > + P_CAM_CC_PLL6_OUT_EVEN, > + P_CAM_CC_PLL7_OUT_EVEN, > + P_CAM_CC_PLL8_OUT_EVEN, > + P_CAM_CC_PLL9_OUT_EVEN, > + P_CAM_CC_PLL9_OUT_ODD, > + P_CAM_CC_PLL10_OUT_EVEN, > + P_CAM_CC_PLL11_OUT_EVEN, > + P_CAM_CC_PLL12_OUT_EVEN, > +}; > + > +static const struct pll_vco lucid_ole_vco[] = { > + { 249600000, 2300000000, 0 }, > +}; > + > +static const struct pll_vco rivian_ole_vco[] = { > + { 777000000, 1285000000, 0 }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll0_config = { > + .l = 0x3e, > + .alpha = 0x8000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00008400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll0 = { > + .offset = 0x0, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll0", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { > + .offset = 0x0, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll0_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll0_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll0.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { > + { 0x2, 3 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { > + .offset = 0x0, > + .post_div_shift = 14, > + .post_div_table = post_div_table_cam_cc_pll0_out_odd, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll0_out_odd", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll0.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll1_config = { > + .l = 0x2f, > + .alpha = 0x6555, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll1 = { > + .offset = 0x1000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll1", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { > + .offset = 0x1000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll1_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll1_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll1.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll2_config = { > + .l = 0x32, > + .alpha = 0x0, > + .config_ctl_val = 0x10000030, > + .config_ctl_hi_val = 0x80890263, > + .config_ctl_hi1_val = 0x00000217, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00100000, > +}; > + > +static struct clk_alpha_pll cam_cc_pll2 = { > + .offset = 0x2000, > + .vco_table = rivian_ole_vco, > + .num_vco = ARRAY_SIZE(rivian_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll2", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_rivian_evo_ops, > + }, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll3_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll3 = { > + .offset = 0x3000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll3", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { > + .offset = 0x3000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll3_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll3_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll3.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll4_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll4 = { > + .offset = 0x4000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll4", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { > + .offset = 0x4000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll4_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll4_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll4.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll5_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll5 = { > + .offset = 0x5000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll5", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { > + .offset = 0x5000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll5_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll5_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll5.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll6_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll6 = { > + .offset = 0x6000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll6", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { > + .offset = 0x6000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll6_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll6_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll6.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll7_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll7 = { > + .offset = 0x7000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll7", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { > + .offset = 0x7000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll7_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll7_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll7.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll8_config = { > + .l = 0x14, > + .alpha = 0xd555, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll8 = { > + .offset = 0x8000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll8", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { > + .offset = 0x8000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll8_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll8_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll8.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll9_config = { > + .l = 0x32, > + .alpha = 0x0, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll9 = { > + .offset = 0x9000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll9", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = { > + .offset = 0x9000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll9_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll9_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll9.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll10_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll10 = { > + .offset = 0xa000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll10", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = { > + .offset = 0xa000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll10_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll10_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll10.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll11_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll11 = { > + .offset = 0xb000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll11", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll11_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll11_out_even = { > + .offset = 0xb000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll11_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll11_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll11_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll11.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct alpha_pll_config cam_cc_pll12_config = { > + .l = 0x30, > + .alpha = 0x8aaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; > + > +static struct clk_alpha_pll cam_cc_pll12 = { > + .offset = 0xc000, > + .vco_table = lucid_ole_vco, > + .num_vco = ARRAY_SIZE(lucid_ole_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll12", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_evo_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_cam_cc_pll12_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv cam_cc_pll12_out_even = { > + .offset = 0xc000, > + .post_div_shift = 10, > + .post_div_table = post_div_table_cam_cc_pll12_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll12_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_pll12_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_pll12.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static const struct parent_map cam_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, > + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, > + { P_CAM_CC_PLL0_OUT_ODD, 3 }, > + { P_CAM_CC_PLL9_OUT_ODD, 4 }, > + { P_CAM_CC_PLL9_OUT_EVEN, 5 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_0[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll0.clkr.hw }, > + { .hw = &cam_cc_pll0_out_even.clkr.hw }, > + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, > + { .hw = &cam_cc_pll9.clkr.hw }, > + { .hw = &cam_cc_pll9_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, > + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_1[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll2.clkr.hw }, > + { .hw = &cam_cc_pll2.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_2[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL8_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_2[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll8_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_3[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_3[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll3_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_4[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL10_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_4[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll10_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_5[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_5[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll4_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_6[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL11_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_6[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll11_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_7[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_7[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll5_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_8[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL12_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_8[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll12_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_9[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_9[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll1_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_10[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_10[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll6_out_even.clkr.hw }, > +}; > + > +static const struct parent_map cam_cc_parent_map_11[] = { > + { P_BI_TCXO, 0 }, > + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data cam_cc_parent_data_11[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &cam_cc_pll7_out_even.clkr.hw }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), > + F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), > + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_bps_clk_src = { > + .cmd_rcgr = 0x10278, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_2, > + .freq_tbl = ftbl_cam_cc_bps_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_bps_clk_src", > + .parent_data = cam_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { > + .cmd_rcgr = 0x13de0, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_camnoc_axi_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_cci_0_clk_src = { > + .cmd_rcgr = 0x13900, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_0_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_cci_1_clk_src = { > + .cmd_rcgr = 0x13a30, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_1_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_cci_2_clk_src = { > + .cmd_rcgr = 0x13b60, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_2_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { > + .cmd_rcgr = 0x11290, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cphy_rx_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { > + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), > + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), > + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_cre_clk_src = { > + .cmd_rcgr = 0x1353c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_cre_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cre_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { > + .cmd_rcgr = 0x15980, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi0phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { > + .cmd_rcgr = 0x15ab8, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi1phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { > + .cmd_rcgr = 0x15bec, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi2phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { > + .cmd_rcgr = 0x15d20, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi3phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_csi4phytimer_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { > + .cmd_rcgr = 0x15e54, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi4phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi4phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { > + .cmd_rcgr = 0x15f88, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi5phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = { > + .cmd_rcgr = 0x160bc, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi6phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = { > + .cmd_rcgr = 0x161f0, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi7phytimer_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { > + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_csid_clk_src = { > + .cmd_rcgr = 0x13ca8, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csid_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csid_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { > + .cmd_rcgr = 0x10018, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_fast_ahb_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), > + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), > + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_icp_clk_src = { > + .cmd_rcgr = 0x137c4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_icp_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_icp_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_0_clk_src = { > + .cmd_rcgr = 0x11018, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_3, > + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_0_clk_src", > + .parent_data = cam_cc_parent_data_3, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_0_dsp_clk_src[] = { > + F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_0_dsp_clk_src = { > + .cmd_rcgr = 0x11154, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_4, > + .freq_tbl = ftbl_cam_cc_ife_0_dsp_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_0_dsp_clk_src", > + .parent_data = cam_cc_parent_data_4, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_1_clk_src = { > + .cmd_rcgr = 0x12018, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_5, > + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_1_clk_src", > + .parent_data = cam_cc_parent_data_5, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src[] = { > + F(466000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_1_dsp_clk_src = { > + .cmd_rcgr = 0x12154, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_6, > + .freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_1_dsp_clk_src", > + .parent_data = cam_cc_parent_data_6, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { > + F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_2_clk_src = { > + .cmd_rcgr = 0x122a8, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_7, > + .freq_tbl = ftbl_cam_cc_ife_2_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_2_clk_src", > + .parent_data = cam_cc_parent_data_7, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src[] = { > + F(466000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ife_2_dsp_clk_src = { > + .cmd_rcgr = 0x123e4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_8, > + .freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_2_dsp_clk_src", > + .parent_data = cam_cc_parent_data_8, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { > + .cmd_rcgr = 0x13000, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csid_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { > + .cmd_rcgr = 0x1313c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_csid_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_csid_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { > + F(455000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), > + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), > + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { > + .cmd_rcgr = 0x103cc, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_9, > + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_nps_clk_src", > + .parent_data = cam_cc_parent_data_9, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), > + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), > + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), > + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_jpeg_clk_src = { > + .cmd_rcgr = 0x13674, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_jpeg_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), > + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_mclk0_clk_src = { > + .cmd_rcgr = 0x15000, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk0_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk1_clk_src = { > + .cmd_rcgr = 0x15130, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk1_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk2_clk_src = { > + .cmd_rcgr = 0x15260, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk2_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk3_clk_src = { > + .cmd_rcgr = 0x15390, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk3_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk4_clk_src = { > + .cmd_rcgr = 0x154c0, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk4_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk5_clk_src = { > + .cmd_rcgr = 0x155f0, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk5_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk6_clk_src = { > + .cmd_rcgr = 0x15720, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk6_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 cam_cc_mclk7_clk_src = { > + .cmd_rcgr = 0x15850, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_1, > + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk7_clk_src", > + .parent_data = cam_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { > + F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_sfe_0_clk_src = { > + .cmd_rcgr = 0x13294, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_10, > + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_0_clk_src", > + .parent_data = cam_cc_parent_data_10, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { > + F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), > + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), > + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), > + F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_sfe_1_clk_src = { > + .cmd_rcgr = 0x133f4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_11, > + .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_1_clk_src", > + .parent_data = cam_cc_parent_data_11, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_11), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { > + .cmd_rcgr = 0x10148, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_slow_ahb_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_branch cam_cc_bps_ahb_clk = { > + .halt_reg = 0x10274, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10274, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_bps_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_bps_clk = { > + .halt_reg = 0x103a4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x103a4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_bps_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_bps_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_bps_fast_ahb_clk = { > + .halt_reg = 0x10144, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10144, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_bps_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_camnoc_axi_clk = { > + .halt_reg = 0x13f0c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13f0c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_camnoc_axi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_camnoc_axi_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cci_0_clk = { > + .halt_reg = 0x13a2c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13a2c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cci_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cci_1_clk = { > + .halt_reg = 0x13b5c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13b5c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cci_1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cci_2_clk = { > + .halt_reg = 0x13c8c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13c8c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cci_2_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cci_2_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_core_ahb_clk = { > + .halt_reg = 0x1406c, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x1406c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_core_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ahb_clk = { > + .halt_reg = 0x13c90, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13c90, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_bps_clk = { > + .halt_reg = 0x103b0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x103b0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_bps_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_bps_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_cre_clk = { > + .halt_reg = 0x1366c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1366c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_cre_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cre_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { > + .halt_reg = 0x13c9c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13c9c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ife_0_clk = { > + .halt_reg = 0x11150, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x11150, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ife_0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ife_1_clk = { > + .halt_reg = 0x12150, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x12150, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ife_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ife_2_clk = { > + .halt_reg = 0x123e0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x123e0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ife_2_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_2_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ife_lite_clk = { > + .halt_reg = 0x13138, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13138, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ife_lite_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_lite_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { > + .halt_reg = 0x10504, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10504, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_ipe_nps_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ipe_nps_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_sbi_clk = { > + .halt_reg = 0x1054c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1054c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_sbi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_sfe_0_clk = { > + .halt_reg = 0x133cc, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x133cc, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_sfe_0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_sfe_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cpas_sfe_1_clk = { > + .halt_reg = 0x1352c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1352c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cpas_sfe_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_sfe_1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cre_ahb_clk = { > + .halt_reg = 0x13670, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13670, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cre_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_cre_clk = { > + .halt_reg = 0x13668, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13668, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_cre_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cre_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi0phytimer_clk = { > + .halt_reg = 0x15aac, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15aac, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi0phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi0phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi1phytimer_clk = { > + .halt_reg = 0x15be4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15be4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi1phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi1phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi2phytimer_clk = { > + .halt_reg = 0x15d18, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15d18, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi2phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi2phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi3phytimer_clk = { > + .halt_reg = 0x15e4c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15e4c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi3phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi3phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi4phytimer_clk = { > + .halt_reg = 0x15f80, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15f80, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi4phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi4phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi5phytimer_clk = { > + .halt_reg = 0x160b4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x160b4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi5phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi5phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi6phytimer_clk = { > + .halt_reg = 0x161e8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x161e8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi6phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi6phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csi7phytimer_clk = { > + .halt_reg = 0x1631c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1631c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csi7phytimer_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csi7phytimer_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csid_clk = { > + .halt_reg = 0x13dd4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13dd4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csid_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_csid_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { > + .halt_reg = 0x15ab4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15ab4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csid_csiphy_rx_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy0_clk = { > + .halt_reg = 0x15ab0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15ab0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy1_clk = { > + .halt_reg = 0x15be8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15be8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy2_clk = { > + .halt_reg = 0x15d1c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15d1c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy2_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy3_clk = { > + .halt_reg = 0x15e50, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15e50, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy3_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy4_clk = { > + .halt_reg = 0x15f84, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x15f84, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy4_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy5_clk = { > + .halt_reg = 0x160b8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x160b8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy5_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy6_clk = { > + .halt_reg = 0x161ec, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x161ec, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy6_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_csiphy7_clk = { > + .halt_reg = 0x16320, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x16320, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_csiphy7_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_drv_ahb_clk = { > + .halt_reg = 0x142d8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x142d8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_drv_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_icp_ahb_clk = { > + .halt_reg = 0x138fc, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x138fc, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_icp_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_icp_clk = { > + .halt_reg = 0x138f0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x138f0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_icp_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_icp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_0_clk = { > + .halt_reg = 0x11144, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x11144, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_0_dsp_clk = { > + .halt_reg = 0x11280, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x11280, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_0_dsp_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_0_dsp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { > + .halt_reg = 0x1128c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1128c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_0_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_1_clk = { > + .halt_reg = 0x12144, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x12144, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_1_dsp_clk = { > + .halt_reg = 0x12280, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x12280, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_1_dsp_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_1_dsp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { > + .halt_reg = 0x1228c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1228c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_1_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_2_clk = { > + .halt_reg = 0x123d4, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x123d4, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_2_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_2_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_2_dsp_clk = { > + .halt_reg = 0x12510, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x12510, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_2_dsp_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_2_dsp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { > + .halt_reg = 0x1251c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1251c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_2_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_lite_ahb_clk = { > + .halt_reg = 0x13278, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13278, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_lite_clk = { > + .halt_reg = 0x1312c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1312c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_lite_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { > + .halt_reg = 0x13274, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13274, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_cphy_rx_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_cphy_rx_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ife_lite_csid_clk = { > + .halt_reg = 0x13268, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13268, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ife_lite_csid_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_lite_csid_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { > + .halt_reg = 0x1051c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1051c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_nps_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_slow_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ipe_nps_clk = { > + .halt_reg = 0x104f8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x104f8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_nps_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ipe_nps_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { > + .halt_reg = 0x10520, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10520, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_nps_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ipe_pps_clk = { > + .halt_reg = 0x10508, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10508, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_pps_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ipe_nps_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { > + .halt_reg = 0x10524, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10524, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_ipe_pps_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_jpeg_1_clk = { > + .halt_reg = 0x137ac, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x137ac, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_jpeg_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_jpeg_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_jpeg_clk = { > + .halt_reg = 0x137a0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x137a0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_jpeg_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_jpeg_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk0_clk = { > + .halt_reg = 0x1512c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1512c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk1_clk = { > + .halt_reg = 0x1525c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1525c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk2_clk = { > + .halt_reg = 0x1538c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1538c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk2_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk2_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk3_clk = { > + .halt_reg = 0x154bc, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x154bc, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk3_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk3_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk4_clk = { > + .halt_reg = 0x155ec, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x155ec, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk4_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk4_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk5_clk = { > + .halt_reg = 0x1571c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1571c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk5_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk5_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk6_clk = { > + .halt_reg = 0x1584c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1584c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk6_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk6_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_mclk7_clk = { > + .halt_reg = 0x1597c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1597c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_mclk7_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_mclk7_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sbi_clk = { > + .halt_reg = 0x10540, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10540, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sbi_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_ife_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sbi_fast_ahb_clk = { > + .halt_reg = 0x10550, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x10550, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sbi_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sfe_0_clk = { > + .halt_reg = 0x133c0, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x133c0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_0_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_sfe_0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { > + .halt_reg = 0x133d8, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x133d8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_0_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sfe_1_clk = { > + .halt_reg = 0x13520, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13520, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_1_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_sfe_1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { > + .halt_reg = 0x13538, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13538, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_sfe_1_fast_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_fast_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc cam_cc_bps_gdsc = { > + .gdscr = 0x10004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_bps_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_ife_0_gdsc = { > + .gdscr = 0x11004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_ife_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_ife_1_gdsc = { > + .gdscr = 0x12004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_ife_1_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_ife_2_gdsc = { > + .gdscr = 0x12294, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_ife_2_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_ipe_0_gdsc = { > + .gdscr = 0x103b8, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_ipe_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_sbi_gdsc = { > + .gdscr = 0x1052c, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_sbi_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_sfe_0_gdsc = { > + .gdscr = 0x13280, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_sfe_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_sfe_1_gdsc = { > + .gdscr = 0x133e0, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_sfe_1_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc cam_cc_titan_top_gdsc = { > + .gdscr = 0x14058, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "cam_cc_titan_top_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > +}; > + > +static struct clk_regmap *cam_cc_sm8550_clocks[] = { > + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, > + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, > + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, > + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, > + [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, > + [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, > + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, > + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, > + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, > + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, > + [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, > + [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, > + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, > + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, > + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, > + [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr, > + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, > + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, > + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, > + [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, > + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, > + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, > + [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, > + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, > + [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, > + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, > + [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, > + [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, > + [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, > + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, > + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, > + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, > + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, > + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, > + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, > + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, > + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, > + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, > + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, > + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, > + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, > + [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr, > + [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr, > + [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr, > + [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr, > + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, > + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, > + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, > + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, > + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, > + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, > + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, > + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, > + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, > + [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr, > + [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr, > + [CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr, > + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, > + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, > + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, > + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, > + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, > + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, > + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, > + [CAM_CC_IFE_0_DSP_CLK_SRC] = &cam_cc_ife_0_dsp_clk_src.clkr, > + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, > + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, > + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, > + [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, > + [CAM_CC_IFE_1_DSP_CLK_SRC] = &cam_cc_ife_1_dsp_clk_src.clkr, > + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, > + [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, > + [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, > + [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, > + [CAM_CC_IFE_2_DSP_CLK_SRC] = &cam_cc_ife_2_dsp_clk_src.clkr, > + [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, > + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, > + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, > + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, > + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, > + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, > + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, > + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, > + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, > + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, > + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, > + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, > + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, > + [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, > + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, > + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, > + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, > + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, > + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, > + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, > + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, > + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, > + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, > + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, > + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, > + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, > + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, > + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, > + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, > + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, > + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, > + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, > + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, > + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, > + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, > + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, > + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, > + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, > + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, > + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, > + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, > + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, > + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, > + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, > + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, > + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, > + [CAM_CC_PLL7] = &cam_cc_pll7.clkr, > + [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, > + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, > + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, > + [CAM_CC_PLL9] = &cam_cc_pll9.clkr, > + [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr, > + [CAM_CC_PLL10] = &cam_cc_pll10.clkr, > + [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr, > + [CAM_CC_PLL11] = &cam_cc_pll11.clkr, > + [CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr, > + [CAM_CC_PLL12] = &cam_cc_pll12.clkr, > + [CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr, > + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, > + [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr, > + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, > + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, > + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, > + [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, > + [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, > + [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, > + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, > +}; > + > +static struct gdsc *cam_cc_sm8550_gdscs[] = { > + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, > + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, > + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, > + [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, > + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, > + [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc, > + [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, > + [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc, > + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, > +}; > + > +static const struct qcom_reset_map cam_cc_sm8550_resets[] = { > + [CAM_CC_BPS_BCR] = { 0x10000 }, > + [CAM_CC_DRV_BCR] = { 0x142d0 }, > + [CAM_CC_ICP_BCR] = { 0x137c0 }, > + [CAM_CC_IFE_0_BCR] = { 0x11000 }, > + [CAM_CC_IFE_1_BCR] = { 0x12000 }, > + [CAM_CC_IFE_2_BCR] = { 0x12290 }, > + [CAM_CC_IPE_0_BCR] = { 0x103b4 }, > + [CAM_CC_QDSS_DEBUG_BCR] = { 0x13f20 }, > + [CAM_CC_SBI_BCR] = { 0x10528 }, > + [CAM_CC_SFE_0_BCR] = { 0x1327c }, > + [CAM_CC_SFE_1_BCR] = { 0x133dc }, > +}; > + > +static const struct regmap_config cam_cc_sm8550_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x16320, > + .fast_io = true, > +}; > + > +static struct qcom_cc_desc cam_cc_sm8550_desc = { > + .config = &cam_cc_sm8550_regmap_config, > + .clks = cam_cc_sm8550_clocks, > + .num_clks = ARRAY_SIZE(cam_cc_sm8550_clocks), > + .resets = cam_cc_sm8550_resets, > + .num_resets = ARRAY_SIZE(cam_cc_sm8550_resets), > + .gdscs = cam_cc_sm8550_gdscs, > + .num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs), > +}; > + > +static const struct of_device_id cam_cc_sm8550_match_table[] = { > + { .compatible = "qcom,sm8550-camcc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table); > + > +static int cam_cc_sm8550_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + ret = devm_pm_runtime_enable(&pdev->dev); > + if (ret) > + return ret; > + > + ret = pm_runtime_resume_and_get(&pdev->dev); > + if (ret) > + return ret; > + > + regmap = qcom_cc_map(pdev, &cam_cc_sm8550_desc); > + if (IS_ERR(regmap)) { > + pm_runtime_put(&pdev->dev); > + return PTR_ERR(regmap); > + } > + > + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); > + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); > + clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); > + > + /* > + * Keep clocks always enabled: > + * cam_cc_gdsc_clk > + * cam_cc_sleep_clk > + */ > + regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); > + > + ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); > + > + pm_runtime_put(&pdev->dev); > + > + return ret; > +} > + > +static struct platform_driver cam_cc_sm8550_driver = { > + .probe = cam_cc_sm8550_probe, > + .driver = { > + .name = "cam_cc-sm8550", > + .of_match_table = cam_cc_sm8550_match_table, > + }, > +}; > + > +module_platform_driver(cam_cc_sm8550_driver); > + > +MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver"); > +MODULE_LICENSE("GPL");