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Date:   Sat, 24 Jun 2023 22:47:17 -0700
From:   Dan Williams <dan.j.williams@intel.com>
To:     Dave Jiang <dave.jiang@intel.com>,
        Terry Bowman <terry.bowman@amd.com>,
        <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
        <ira.weiny@intel.com>, <bwidawsk@kernel.org>,
        <dan.j.williams@intel.com>, <Jonathan.Cameron@huawei.com>,
        <linux-cxl@vger.kernel.org>
CC:     <rrichter@amd.com>, <linux-kernel@vger.kernel.org>,
        <bhelgaas@google.com>
Subject: Re: [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected
 errors to the CXL.mem dev handler
Message-ID: <6497d4e5e9cb_2ed729496@dwillia2-xfh.jf.intel.com.notmuch>
References: <20230622205523.85375-1-terry.bowman@amd.com>
 <20230622205523.85375-26-terry.bowman@amd.com>
 <98a0e78c-5b78-136e-f955-0d8680c3c6b0@intel.com>
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Dave Jiang wrote:
> 
> 
> On 6/22/23 13:55, Terry Bowman wrote:
> > From: Robert Richter <rrichter@amd.com>
> > 
> > In Restricted CXL Device (RCD) mode a CXL device is exposed as an
> > RCiEP, but CXL downstream and upstream ports are not enumerated and
> > not visible in the PCIe hierarchy. [1] Protocol and link errors from
> > these non-enumerated ports are signaled as internal AER errors, either
> > Uncorrectable Internal Error (UIE) or Corrected Internal Errors (CIE)
> > via an RCEC.
> > 
> > Restricted CXL host (RCH) downstream port-detected errors have the
> > Requster ID of the RCEC set in the RCEC's AER Error Source ID
> 
> s/Requster/Requester/

Thanks, fixed.