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This > implementation comes with drawbacks: During ACPI table scan there is > already MMIO access including mapping and unmapping, but only ACPI > data should be collected here. The collected data must be transferred > through a couple of interfaces until it is finally consumed when > creating the dport. This causes complex data structures and function > interfaces. Additionally, RCRB parsing will be extended to also > extract AER data, it would be much easier do this at a later point > during port and dport creation when the data structures are available > to hold that data. > > To simplify all that, probe the RCRB at a later point during RCH > downstream port creation. Change ACPI table parser to only extract the > base address of either the component registers or the RCRB. Parse and > extract the RCRB in devm_cxl_add_rch_dport(). > > This is in preparation to centralize all RCRB scanning. This patch by itself causes cxl_test build bisection breakage: depmod: ERROR: Cycle detected: cxl_mock -> cxl_core -> cxl_mock depmod: ERROR: Cycle detected: encrypted_keys depmod: ERROR: Found 2 modules in dependency cycles! make: *** [Makefile:1956: modules_install] Error 1 ...so I will just squash it with the next patch and add a co-developed-by.