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References: <20230607201641.20982-1-ddrokosov@sberdevices.ru> <20230607201641.20982-7-ddrokosov@sberdevices.ru>
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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Sun, 25 Jun 2023 23:11:40 +0200
Message-ID: <CAFBinCC_g6FhzR=PNDsYwT4OZb4uAXAWYGKSe7vSX7_pWM8pNA@mail.gmail.com>
Subject: Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins
To:     Dmitry Rokosov <ddrokosov@sberdevices.ru>
Cc:     neil.armstrong@linaro.org, jbrunet@baylibre.com,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com,
        conor+dt@kernel.org, kernel@sberdevices.ru,
        sdfw_system_team@sberdevices.ru, rockosov@gmail.com,
        linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        Jan Dakinevich <yvdakinevich@sberdevices.ru>
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On Wed, Jun 7, 2023 at 10:16=E2=80=AFPM Dmitry Rokosov <ddrokosov@sberdevic=
es.ru> wrote:
>
> From: Jan Dakinevich <yvdakinevich@sberdevices.ru>
>
> The definition is inspired by a similar one for AXG SoC family.
> 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
> "default" and "clk-gate" in board-specific device trees.
Let's wait for Neil's response on the other patch for the question
about pin mux settings

> 'meson-gx' driver during initialization sets clock to safe low-frequency
> value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
> high-frequency by default, and using of eMMC's internal divider is not
> enough to achieve so low values. To provide low-frequency source,
> reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
Even if the pinctrl part should be postponed then I think it's worth
adding &sd_emmc