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CC:     Pankaj Gupta <pankaj.gupta@nxp.com>, Varun Sethi <V.Sethi@nxp.com>
Subject: [PATCH v2] arm64: dts: imx8ulp-evk: add caam jr
Thread-Topic: [PATCH v2] arm64: dts: imx8ulp-evk: add caam jr
Thread-Index: AQHZp+k2v8Jbz02GhkGV+zbcgHYc4w==
Date:   Mon, 26 Jun 2023 04:46:46 +0000
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------------------------------------------------


Add crypto node in device tree for:
- CAAM job-ring

Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d=
ts/freescale/imx8ulp.dtsi
index 32193a43ff49..ce8de81cac9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 {
 				#reset-cells =3D <1>;
 			};
=20
+			crypto: crypto@292e0000 {
+				compatible =3D "fsl,sec-v4.0";
+				#address-cells =3D <1>;
+				#size-cells =3D <1>;
+				reg =3D <0x292e0000 0x10000>;
+				ranges =3D <0 0x292e0000 0x10000>;
+
+				sec_jr0: jr@1000 {
+					compatible =3D "fsl,sec-v4.0-job-ring";
+					reg =3D <0x1000 0x1000>;
+					interrupts =3D <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr@2000 {
+					compatible =3D "fsl,sec-v4.0-job-ring";
+					reg =3D <0x2000 0x1000>;
+					interrupts =3D <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible =3D "fsl,sec-v4.0-job-ring";
+					reg =3D <0x3000 0x1000>;
+					interrupts =3D <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr3: jr@4000 {
+					compatible =3D "fsl,sec-v4.0-job-ring";
+					reg =3D <0x4000 0x1000>;
+					interrupts =3D <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			tpm5: tpm@29340000 {
 				compatible =3D "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
 				reg =3D <0x29340000 0x1000>;
--=20
2.34.1