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Message-ID: <e5c412a0-a3e9-9938-d767-96364cde0e7e@linaro.org>
Date:   Mon, 26 Jun 2023 14:33:58 +0200
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To:     Mohammad Rafi Shaik <quic_mohs@quicinc.com>,
        krzysztof.kozlowski+dt@linaro.org, swboyd@chromium.org,
        andersson@kernel.org, broonie@kernel.org, agross@kernel.org
Cc:     robh+dt@kernel.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        quic_rohkumar@quicinc.com, srinivas.kandagatla@linaro.org,
        dianders@chromium.org, judyhsiao@chromium.org,
        quic_visr@quicinc.com,
        Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
References: <20230616103534.4031331-1-quic_mohs@quicinc.com>
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 <20ec31b3-667a-0617-71d4-586789e2c2a4@quicinc.com>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: Re: [RESEND v6 8/8] arm64: dts: qcom: sc7280: Add qcom,adsp-pil-mode
 property in clock nodes
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On 26.06.2023 13:17, Mohammad Rafi Shaik wrote:
> 
> On 6/16/2023 5:06 PM, Konrad Dybcio wrote:
>> On 16.06.2023 12:35, Mohammad Rafi Shaik wrote:
>>> From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>>>
>>> Add "qcom,adsp-pil-mode" property in clock nodes for herobrine
>>> crd revision 3 board specific device tree.
>>> This is to register clocks conditionally by differentiating ADSP
>>> based platforms and legacy path platforms.
>>> Also disable lpass_core clock, as it is creating conflict
>>> with ADSP clocks and it is not required for ADSP based platforms.
>>>
>>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>>> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
>>> ---
>>>   .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi    | 12 ++++++++++++
>>>   1 file changed, 12 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>>> index c02ca393378f..876a29178d46 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>>> @@ -197,6 +197,14 @@ q6prmcc: clock-controller {
>>>       };
>>>   };
>>>   +&lpass_aon {
>>> +    qcom,adsp-pil-mode;
>> That's a whole bunch of hacky bindings that makes no sense..
>>
>> What should have been done from the beginning is:
>>
>> - all clocks should be registered inside the clock driver, unconditionally
>>    as far as .c code is concerned
>>
>> - the regmap properties within should reflect the actual max register
>>    range within the hardware block
>>
>> - device-tree should contain protected-clocks, which omits registering
>>    specified clks (I guess in the ADSP-less case you could probably even
>>    register all of them and it wouldn't hurt)
>>
> For AR solution, it is required to add "qcom,adsp-pil-mode" flag to enable ahbm and ahbs clocks.
> Please refer: https://elixir.bootlin.com/linux/v6.4-rc7/source/drivers/clk/qcom/lpassaudiocc-sc7280.c
It does what I've just said, except in an implementation-specific way,
instead of using an existing, common DT property.

Konrad

>>> +};
>>> +
>>> +&lpass_core {
>>> +    status = "disabled";
>> status = "reserved";
>>
>> Konrad
> Okay, will change status flag.
> 
> Rafi
>>> +};
>>> +
>>>   &lpass_rx_macro {
>>>       /delete-property/ power-domains;
>>>       /delete-property/ power-domain-names;
>>> @@ -239,3 +247,7 @@ &lpass_va_macro {
>>>         status = "okay";
>>>   };
>>> +
>>> +&lpasscc {
>>> +    qcom,adsp-pil-mode;
>>> +};