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Date:   Mon, 26 Jun 2023 09:16:28 -0500
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Subject: Re: [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register
 mappings in struct cxl_dev_state
To:     Dan Williams <dan.j.williams@intel.com>,
        alison.schofield@intel.com, vishal.l.verma@intel.com,
        ira.weiny@intel.com, bwidawsk@kernel.org, dave.jiang@intel.com,
        Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org
Cc:     rrichter@amd.com, linux-kernel@vger.kernel.org, bhelgaas@google.com
References: <20230622205523.85375-1-terry.bowman@amd.com>
 <20230622205523.85375-17-terry.bowman@amd.com>
 <64987b92ce13c_2ed7294f4@dwillia2-xfh.jf.intel.com.notmuch>
Content-Language: en-US
From:   Terry Bowman <Terry.Bowman@amd.com>
In-Reply-To: <64987b92ce13c_2ed7294f4@dwillia2-xfh.jf.intel.com.notmuch>
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Hi Dan,

On 6/25/23 12:38, Dan Williams wrote:
> Terry Bowman wrote:
>> From: Robert Richter <rrichter@amd.com>
>>
>> Same as for ports and dports, also store the endpoint's Component
>> Register mappings, use struct cxl_dev_state for that.
>>
>> The Component Register base address @component_reg_phys is no longer
>> used after the rework of the Component Register setup which now uses
>> struct member @comp_map instead. Remove the base address.
>>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> Starting with this patch my QEMU cxl configuration fails to probe the
> device:
> 
> # cxl list -Miu
> {
>   "memdev":"mem0",
>   "pmem_size":"512.00 MiB (536.87 MB)",
>   "serial":"0",
>   "host":"0000:35:00.0",
>   "state":"disabled"
> }
> 
> ...the next patch changes where the failure occurs, but it still fails
> and applying the rest of the patches does not fix the issue either. I
> have not had the time to debug it. Please have a look and make sure that
> at every step of this patch set the driver is still operational. I.e.
> 'git bisect' should never find this conversion in a broken state.
> 

Yes, we will look into this issue now. We will verify each patch 
builds and runs without degrading. Can you share which Qemu release/branch
to test against?

> For now I will look at proceeding with patch 1-15.
> 

Ok

Regards,
Terry

> The cxl bits of my QEMU config are:
> 
>   -object memory-backend-file,id=cxl-mem1,share=on,mem-path=cxl-window1,size=$cxl_backend_size
>   -object memory-backend-file,id=cxl-label1,share=on,mem-path=cxl-label1,size=$cxl_label_size
>   -device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52
>   -device cxl-rp,id=rp0,bus=cxl.0,addr=0.0,chassis=0,slot=0,port=0
>   -device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,lsa=cxl-label1
>   -M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G