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References: <20230623222016.3742145-1-evan@rivosinc.com> <tencent_817CE182DEDA938E03B848314821098D4408@qq.com>
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From:   Evan Green <evan@rivosinc.com>
Date:   Mon, 26 Jun 2023 12:48:42 -0700
Message-ID: <CALs-Hsv+iS055GUJdotYxmn5ST9y9yT7P1PiG4DLPU+rzPO20A@mail.gmail.com>
Subject: Re: [PATCH 0/2] RISC-V: Probe for misaligned access speed
To:     Yangyu Chen <cyy@cyyself.name>
Cc:     ajones@ventanamicro.com, alexghiti@rivosinc.com,
        andy.chiu@sifive.com, aou@eecs.berkeley.edu,
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On Sat, Jun 24, 2023 at 3:22=E2=80=AFAM Yangyu Chen <cyy@cyyself.name> wrot=
e:
>
> Hi,
>
> Thanks for doing this.
>
> On 6/24/23 6:20 AM, Evan Green wrote:
> > I don't have a machine where misaligned accesses are slow, but I'd be
> > interested to see the results of booting this series if someone did.
>
> I have tested your patches on a 100MHz BigCore rocket-chip with opensbi r=
unning on FPGA with 72bit(64bit+ECC) DDR3 1600MHz memory. As the rocket-chi=
p did not support misaligned memory access, every misaligned memory access =
will trap and emulated by SBI.
>
> Here is the result:
>
> ~ # cat /proc/cpuinfo
> processor       : 0
> hart            : 0
> isa             : rv64imafdc
> mmu             : sv39
> uarch           : sifive,rocket0
> mvendorid       : 0x0
> marchid         : 0x1
> mimpid          : 0x20181004
>
> processor       : 1
> hart            : 1
> isa             : rv64imafdc
> mmu             : sv39
> uarch           : sifive,rocket0
> mvendorid       : 0x0
> marchid         : 0x1
> mimpid          : 0x20181004
>
> ~ # dmesg | grep Unaligned
> [    0.210140] cpu1: Unaligned word copy 0 MB/s, byte copy 38 MB/s, misal=
igned accesses are slow
> [    0.410715] cpu0: Unaligned word copy 0 MB/s, byte copy 35 MB/s, misal=
igned accesses are slow

Thank you, Yangyu! Oof, the firmware traps are quite slow!
-Evan