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Date:   Tue, 27 Jun 2023 08:08:09 +0200
From:   Michael Walle <michael@walle.cc>
To:     Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc:     tudor.ambarus@linaro.org, pratyush@kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, git@amd.com, linux-mtd@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        amitrkcian2002@gmail.com,
        Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Subject: Re: [PATCH v3 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property
 to avoid setting SRWD bit in status register
In-Reply-To: <20230625100251.31589-2-amit.kumar-mahapatra@amd.com>
References: <20230625100251.31589-1-amit.kumar-mahapatra@amd.com>
 <20230625100251.31589-2-amit.kumar-mahapatra@amd.com>
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Am 2023-06-25 12:02, schrieb Amit Kumar Mahapatra:
> If the WP# signal of the flash device is either not connected or is 
> wrongly
> tied to GND (that includes internal pull-downs), and the software sets 
> the
> status register write disable (SRWD) bit in the status register then 
> the
> status register permanently becomes read-only. To avoid this added a 
> new
> boolean DT property "no-wp". If this property is set in the DT then the
> software avoids setting the SRWD during status register write 
> operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
> As the DT property name has changed so, removed Reviewed-by tag.
> @Cornor if possible, could you please review this updated patch.
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml 
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..97344969b02d 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable 
> reset
>        mechanism.
> 
> +  no-wp:
> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, 
> combined
> +      with the WP# signal, provides hardware data protection for the 
> device. When
> +      the SRWD bit is set to 1, and the WP# signal is either driven 
> LOW or hard
> +      strapped to LOW, the status register nonvolatile bits become 
> read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only 
> way to exit
> +      this hardware-protected mode is to drive WP# HIGH. If the WP# 
> signal of the
> +      flash device is not connected or is wrongly tied to GND (that 
> includes internal
> +      pull-downs) then status register permanently becomes read-only 
> as the SRWD bit
> +      cannot be reset. This boolean flag can be used on such systems 
> to avoid setting
> +      the SRWD bit while writing the status register. WP# signal hard 
> strapped to GND
> +      can be a valid use case.
> +

Sounds good! Thank you.

Reviewed-by: Michael Walle <michael@walle.cc>

-michael