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From:   Samuel Ortiz <sameo@rivosinc.com>
To:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org
Cc:     Samuel Ortiz <sameo@rivosinc.com>, linux@rivosinc.com,
        Conor Dooley <conor.dooley@microchip.com>,
        Andrew Jones <ajones@ventanamicro.com>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>,
        Anup Patel <apatel@ventanamicro.com>,
        linux-kernel@vger.kernel.org,
        "Hongren (Zenithal) Zheng" <i@zenithal.me>,
        Guo Ren <guoren@kernel.org>, Atish Patra <atishp@rivosinc.com>,
        =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= <bjorn@rivosinc.com>,
        Evan Green <evan@rivosinc.com>
Subject: [PATCH 0/3] RISC-V: archrandom support
Date:   Tue, 27 Jun 2023 16:37:41 +0200
Message-ID: <20230627143747.1599218-1-sameo@rivosinc.com>
MIME-Version: 1.0
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Precedence: bulk

This patchset adds support for the archrandom API to the RISC-V
architecture.

The ratified crypto scalar extensions provide entropy bits via the seed
CSR, as exposed by the Zkr extension.

The first patch of this patchset allows for detecting support of the Zbc
and all scalar crypto extensions.

The second patch exposes the Zbc and scalar crypto extensions through
the hwprobe syscall.

The last patch relies on the first ones to check for the Zkr support,
and implements get_random_seed_longs by looping through a seed CSR
read-write to return one long worth of entropy.

Hongren (Zenithal) Zheng (1):
  RISC-V: add Bitmanip/Scalar Crypto parsing from DT

Samuel Ortiz (2):
  RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions
  RISC-V: Implement archrandom when Zkr is available

 Documentation/riscv/hwprobe.rst       | 33 ++++++++++++++
 arch/riscv/include/asm/archrandom.h   | 66 +++++++++++++++++++++++++++
 arch/riscv/include/asm/csr.h          |  9 ++++
 arch/riscv/include/asm/hwcap.h        | 11 +++++
 arch/riscv/include/uapi/asm/hwprobe.h | 11 +++++
 arch/riscv/kernel/cpu.c               | 11 +++++
 arch/riscv/kernel/cpufeature.c        | 30 ++++++++++++
 arch/riscv/kernel/sys_riscv.c         | 36 +++++++++------
 8 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 arch/riscv/include/asm/archrandom.h


base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3
-- 
2.41.0