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Date:   Tue, 27 Jun 2023 20:37:18 +0530
From:   Manivannan Sadhasivam <mani@kernel.org>
To:     Pavan Kondeti <quic_pkondeti@quicinc.com>
Cc:     Krishna chaitanya chundru <quic_krichai@quicinc.com>,
        manivannan.sadhasivam@linaro.org, helgaas@kernel.org,
        linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com,
        quic_nitegupt@quicinc.com, quic_skananth@quicinc.com,
        quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v5 3/3] PCI: qcom-ep: Add ICC bandwidth voting support
Message-ID: <20230627150718.GJ5490@thinkpad>
References: <1687827692-6181-1-git-send-email-quic_krichai@quicinc.com>
 <1687827692-6181-4-git-send-email-quic_krichai@quicinc.com>
 <bdce0719-4f12-4e75-a8e7-1b38d269ac15@quicinc.com>
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On Tue, Jun 27, 2023 at 12:05:23PM +0530, Pavan Kondeti wrote:
> On Tue, Jun 27, 2023 at 06:31:31AM +0530, Krishna chaitanya chundru wrote:
> > +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
> > +{
> > +	struct dw_pcie *pci = &pcie_ep->pci;
> > +	u32 offset, status, bw;
> > +	int speed, width;
> > +	int ret;
> > +
> > +	if (!pcie_ep->icc_mem)
> > +		return;
> > +
> 
> Is this check needed? interconnect is added as required property and
> probe is failed if interconnect get fails. qcom_pcie_enable_resources()
> which gets called before enabling this interrupt is assuming that
> interconnect available.
> 

Even though the current binding requires interconnect, driver needs to be
backwards compatible with old dts where there was no interconnect.

Also, devm_of_icc_get() will return NULL if the property is missing in dts. But
we are just checking for IS_ERR not IS_ERR_OR_NULL. So this check is required.

- Mani

> 
> > +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +	status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
> > +
> > +	speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
> > +	width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
> > +
> > +	switch (speed) {
> > +	case 1:
> > +		bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);
> > +		break;
> > +	case 2:
> > +		bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);
> > +		break;
> > +	case 3:
> > +		bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);
> > +		break;
> > +	default:
> > +		dev_warn(pci->dev, "using default GEN4 bandwidth\n");
> > +		fallthrough;
> > +	case 4:
> > +		bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);
> > +		break;
> > +	}
> > +
> > +	ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);
> > +	if (ret) {
> > +		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
> > +			ret);
> > +	}
> 
> Are you not seeing the below warning from checkpatch?
> 
> WARNING: braces {} are not necessary for single statement blocks
> 
> > +}
> > +
> >  static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
> >  {
> >  	int ret;
> > +	struct dw_pcie *pci = &pcie_ep->pci;
> >  
> >  	ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
> >  	if (ret)
> > @@ -277,6 +331,20 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
> >  	if (ret)
> >  		goto err_phy_exit;
> >  
> > +	/*
> > +	 * Some Qualcomm platforms require interconnect bandwidth constraints
> > +	 * to be set before enabling interconnect clocks.
> > +	 *
> > +	 * Set an initial peak bandwidth corresponding to single-lane Gen 1
> > +	 * for the pcie-mem path.
> > +	 */
> > +	ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));
> > +	if (ret) {
> > +		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
> > +			ret);
> > +		goto err_phy_exit;
> > +	}
> > +
> >  	return 0;
> 
> Thanks,
> Pavan

-- 
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