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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 28 Jun 2023 13:57:40 +0100
Message-ID: <CA+V-a8tMcNnx3AK69KeFaNLvgt4yhy0wKdKdjR=AvuUwZNM-RA@mail.gmail.com>
Subject: Re: [PATCH v9 5/6] cache: Add L2 cache management for Andes AX45MP
 RISC-V core
To:     Arnd Bergmann <arnd@arndb.de>
Cc:     "Conor.Dooley" <conor.dooley@microchip.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        guoren <guoren@kernel.org>,
        Andrew Jones <ajones@ventanamicro.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Samuel Holland <samuel@sholland.org>,
        linux-riscv@lists.infradead.org,
        Christoph Hellwig <hch@infradead.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Arnd,

Thank you for the review.


On Wed, Jun 14, 2023 at 2:11=E2=80=AFPM Arnd Bergmann <arnd@arndb.de> wrote=
:
>
> On Wed, Jun 14, 2023, at 12:47, Prabhakar wrote:
>
> > +static void ax45mp_dma_cache_inv(phys_addr_t paddr, unsigned long size=
)
> > +{
> > +     unsigned long start =3D (unsigned long)phys_to_virt(paddr);
> > +     char cache_buf[2][AX45MP_CACHE_LINE_SIZE];
> > +     unsigned long end =3D start + size;
> > +     unsigned long old_start =3D start;
> > +     unsigned long old_end =3D end;
> > +     unsigned long line_size;
> > +     unsigned long flags;
> > +
> > +     if (unlikely(start =3D=3D end))
> > +             return;
> > +
> > +     line_size =3D ax45mp_priv.ax45mp_cache_line_size;
> > +
> > +     memset(&cache_buf, 0x0, sizeof(cache_buf));
> > +     start =3D start & (~(line_size - 1));
> > +     end =3D ((end + line_size - 1) & (~(line_size - 1)));
> > +
> > +     local_irq_save(flags);
> > +     if (unlikely(start !=3D old_start))
> > +             memcpy(&cache_buf[0][0], (void *)start, line_size);
> > +
> > +     if (unlikely(end !=3D old_end))
> > +             memcpy(&cache_buf[1][0], (void *)(old_end & (~(line_size =
- 1))),
> > line_size);
> > +
> > +     ax45mp_cpu_dcache_inval_range(start, end, line_size);
> > +
> > +     if (unlikely(start !=3D old_start))
> > +             memcpy((void *)start, &cache_buf[0][0], (old_start & (lin=
e_size -
> > 1)));
> > +
> > +     local_irq_restore(flags);
> > +}
>
> I'm not quite sure what this does, maybe some comments would help.
>
> This looks like a novel method of preserving partial cache lines
> at the beginning (but not the end?) of an unaligned area.
>
I missed this earlier, (I removed the preserving of cache line from
then end and left the beginning part. Samuel pointed to earlier on
these patches if the cache-line-size is 64 we dont need to do this).
Preserving cache lines is not needed at all,  Ive verified this and
just doing a _inval() is sufficient. I'll update this and send a new
version.

Cheers,
Prabhakar

> As far as I can tell, most dma_mapping implementations don't
> even try to do that at all, but the ones that do take a different
> approach by calling _wback_inv() on partial cache lines instead
> of calling _inv().
>
> I'd say this does not belong into the low-level operations
> here, especially since the ZICBOM variant doesn't do this either.
>

>       Arnd