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Message-ID: <0dd16ca1-9377-30e4-3f5f-3ce96d9db1c6@amlogic.com>
Date:   Thu, 29 Jun 2023 15:36:03 +0800
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Subject: Re: [PATCH v6 4/4] arm64: dts: amlogic-t7-a311d2-khadas-vim4: add
 initial device-tree
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To:     tanure@linux.com
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Kevin Hilman <khilman@baylibre.com>, Nick <nick@khadas.com>,
        Artem <art@khadas.com>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org
References: <20230627091007.190958-1-tanure@linux.com>
 <20230627091007.190958-5-tanure@linux.com>
 <fd7e60d1-b99a-a425-42c9-db85236ba71e@amlogic.com>
 <CAJX_Q+1q1nbE3HxA_xG5f6vwRBfvzcfBnXiFnEfsU7KuBkTHWA@mail.gmail.com>
From:   Xianwei Zhao <xianwei.zhao@amlogic.com>
In-Reply-To: <CAJX_Q+1q1nbE3HxA_xG5f6vwRBfvzcfBnXiFnEfsU7KuBkTHWA@mail.gmail.com>
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On 2023/6/29 15:10, Lucas Tanure wrote:
> [ EXTERNAL EMAIL ]
> 
> On Tue, Jun 27, 2023 at 10:21 AM Xianwei Zhao <xianwei.zhao@amlogic.com> wrote:
>>
>>
>>
>> On 2023/6/27 17:10, Lucas Tanure wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> The Khadas VIM4 uses the Amlogic A311D2 SoC, based on the Amlogic T7 SoC
>>> family, on a board with the same form factor as the VIM3 models.
>>>
>>> - 8GB LPDDR4X 2016MHz
>>> - 32GB eMMC 5.1 storage
>>> - 32MB SPI flash
>>> - 10/100/1000 Base-T Ethernet
>>> - AP6275S Wireless (802.11 a/b/g/n/ac/ax, BT5.1)
>>> - HDMI 2.1 video
>>> - HDMI Input
>>> - 1x USB 2.0 + 1x USB 3.0 ports
>>> - 1x USB-C (power) with USB 2.0 OTG
>>> - 3x LED's (1x red, 1x blue, 1x white)
>>> - 3x buttons (power, function, reset)
>>> - M2 socket with PCIe, USB, ADC & I2C
>>> - 40pin GPIO Header
>>> - 1x micro SD card slot
>>>
>>> Signed-off-by: Lucas Tanure <tanure@linux.com>
>>> ---
>>>    arch/arm64/boot/dts/amlogic/Makefile          |   1 +
>>>    .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts |  52 ++++++
>>>    arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi   | 158 ++++++++++++++++++
>>>    3 files changed, 211 insertions(+)
>>>    create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>>>    create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
>>> index cd1c5b04890a..166fec1e4229 100644
>>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>>> @@ -1,4 +1,5 @@
>>>    # SPDX-License-Identifier: GPL-2.0
>>> +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
>>>    dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
>>>    dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb
>>>    dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>>> new file mode 100644
>>> index 000000000000..5d7fb86a9738
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>>> @@ -0,0 +1,52 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Copyright (c) 2022 Wesion, Inc. All rights reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "amlogic-t7.dtsi"
>>> +
>>> +/ {
>>> +       model = "Khadas vim4";
>>> +       compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";
>>> +
>>> +       aliases {
>>> +               serial0 = &uart_A;
>>> +       };
>>> +
>>> +       memory@0 {
>>> +               device_type = "memory";
>>> +               reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
>>> +       };
>>> +
>>> +       reserved-memory {
>>> +               #address-cells = <2>;
>>> +               #size-cells = <2>;
>>> +               ranges;
>>> +
>>> +               /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
>>> +               secmon_reserved: secmon@5000000 {
>>> +                       reg = <0x0 0x05000000 0x0 0x300000>;
>>> +                       no-map;
>>> +               };
>>> +
>>> +               /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
>>> +               secmon_reserved_bl32: secmon@5300000 {
>>> +                       reg = <0x0 0x05300000 0x0 0x2000000>;
>>> +                       no-map;
>>> +               };
>>> +       };
>>> +
>>> +       xtal: xtal-clk {
>>> +               compatible = "fixed-clock";
>>> +               clock-frequency = <24000000>;
>>> +               clock-output-names = "xtal";
>>> +               #clock-cells = <0>;
>>> +       };
>>> +
>>> +};
>>> +
>>> +&uart_A {
>>> +       status = "okay";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> new file mode 100644
>>> index 000000000000..6f3971b4df99
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> @@ -0,0 +1,158 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +       interrupt-parent = <&gic>;
>>> +       #address-cells = <2>;
>>> +       #size-cells = <2>;
>>> +
>>> +       cpus {
>>> +               #address-cells = <0x2>;
>>> +               #size-cells = <0x0>;
>>> +
>>> +               cpu-map {
>>> +                       cluster0 {
>>> +                               core0 {
>>> +                                       cpu = <&cpu100>;
>>> +                               };
>>> +                               core1 {
>>> +                                       cpu = <&cpu101>;
>>> +                               };
>>> +                               core2 {
>>> +                                       cpu = <&cpu102>;
>>> +                               };
>>> +                               core3 {
>>> +                                       cpu = <&cpu103>;
>>> +                               };
>>> +                       };
>>> +
>>> +                       cluster1 {
>>> +                               core0 {
>>> +                                       cpu = <&cpu0>;
>>> +                               };
>>> +                               core1 {
>>> +                                       cpu = <&cpu1>;
>>> +                               };
>>> +                               core2 {
>>> +                                       cpu = <&cpu2>;
>>> +                               };
>>> +                               core3 {
>>> +                                       cpu = <&cpu3>;
>>> +                               };
>>> +                       };
>>> +               };
>>> +
>>> +               cpu100: cpu@100 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a53";
>>> +                       reg = <0x0 0x100>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu101: cpu@101{
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a53";
>>> +                       reg = <0x0 0x101>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu102: cpu@102 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a53";
>>> +                       reg = <0x0 0x102>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu103: cpu@103 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a53";
>>> +                       reg = <0x0 0x103>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu0: cpu@0 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a73";
>>> +                       reg = <0x0 0x0>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu1: cpu@1 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a73";
>>> +                       reg = <0x0 0x1>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu2: cpu@2 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a73";
>>> +                       reg = <0x0 0x2>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +
>>> +               cpu3: cpu@3 {
>>> +                       device_type = "cpu";
>>> +                       compatible = "arm,cortex-a73";
>>> +                       reg = <0x0 0x3>;
>>> +                       enable-method = "psci";
>>> +               };
>>> +       };
>>> +
>>> +       timer {
>>> +               compatible = "arm,armv8-timer";
>>> +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>> +       };
>> cpu number is 8, not 4, need use GIC_CPU_MASK_SIMPLE(8)
>>> +
>>> +       psci {
>>> +               compatible = "arm,psci-1.0";
>>> +               method = "smc";
>>> +       };
>>> +
>>> +       sm: secure-monitor {
>>> +               compatible = "amlogic,meson-gxbb-sm";
>>> +       };
>>> +
>>> +       soc {
>>> +               compatible = "simple-bus";
>>> +               #address-cells = <2>;
>>> +               #size-cells = <2>;
>>> +               ranges;
>>> +
>>> +               gic: interrupt-controller@fff01000 {
>>> +                       compatible = "arm,gic-400";
>>> +                       #interrupt-cells = <3>;
>>> +                       #address-cells = <0>;
>>> +                       interrupt-controller;
>>> +                       reg = <0x0 0xfff01000 0 0x1000>,
>>> +                             <0x0 0xfff02000 0 0x0100>;
>>> +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> cpu number is 8, not 4, need use GIC_CPU_MASK_SIMPLE(8)
> OK
> 
>>> +               };
>>> +
>>> +               apb4: bus@fe000000 {
>>> +                       compatible = "simple-bus";
>>> +                       reg = <0x0 0xfe000000 0x0 0x480000>;
>>> +                       #address-cells = <2>;
>>> +                       #size-cells = <2>;
>>> +                       ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>>> +
>>> +                       uart_A: serial@78000 {
>> use lowercase, "uart_a"
> 
> OK
>>> +                               compatible = "amlogic,t7-uart",
>>> +                                            "amlogic,meson-s4-uart";
>>> +                               reg = <0x0 0x78000 0x0 0x18>;
>>> +                               interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>>> +                               status = "disabled";
>>> +                               clocks = <&xtal>, <&xtal>, <&xtal>
>> "xtal" why defined in  amlogic-t7-a311d2-khadas-vim4.dts files
> 
> The 24MHz clock is a crystal in VIm4 schematic, so its something the
> board did to provide that clock.
> Other boards using a311d2 could provide that clock in a different way.
> Or are you saying that this clock is mandatory at boot time, and all
> boards using this chip will have the same crystal?The board must use crystal, different boards maybe use different 
frequency. DTSI file be included by other DTS or DTSI files.
It is strange that DTSI file reference DTS file's  property .
The property "xtal" can  be defined in DTSI file, DTS file can Change 
the "frequency" if necessary, like other property.
> 
>>> +                               clock-names = "xtal", "pclk", "baud";
>>> +                       };
>>> +               };
>>> +
>>> +       };
>>> +};
>>> --
>>> 2.41.0
>>>