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From:   Evan Green <evan@rivosinc.com>
Date:   Thu, 29 Jun 2023 16:10:48 -0700
Message-ID: <CALs-HstMTxJFHEoSCaAUtYzT+a-2RSYAhWMQmkVw2+WE=y0agQ@mail.gmail.com>
Subject: Re: [PATCH v2 01/10] RISC-V: don't parse dt/acpi isa string to get rv32/rv64
To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     palmer@dabbelt.com, conor@kernel.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Andrew Jones <ajones@ventanamicro.com>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>,
        Sunil V L <sunilvl@ventanamicro.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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On Thu, Jun 29, 2023 at 1:29=E2=80=AFAM Conor Dooley <conor.dooley@microchi=
p.com> wrote:
>
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> When filling hwcap the kernel already expects the isa string to start wit=
h
> rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT.
>
> So when recreating the runtime isa-string we can also just go the other w=
ay
> to get the correct starting point for it.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Changes in v2:
> - Delete the whole else & pull print_mmu() above it, since that's common
>   code now
> ---
>  arch/riscv/kernel/cpu.c | 21 +++++++++------------
>  1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index a2fc952318e9..2fb5e8e1df52 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -253,13 +253,16 @@ static void print_isa_ext(struct seq_file *f)
>   */
>  static const char base_riscv_exts[13] =3D "imafdqcbkjpvh";
>
> -static void print_isa(struct seq_file *f, const char *isa)
> +static void print_isa(struct seq_file *f)
>  {
>         int i;
>
>         seq_puts(f, "isa\t\t: ");
> -       /* Print the rv[64/32] part */
> -       seq_write(f, isa, 4);
> +       if (IS_ENABLED(CONFIG_32BIT))
> +               seq_write(f, "rv32", 4);
> +       else
> +               seq_write(f, "rv64", 4);
> +
>         for (i =3D 0; i < sizeof(base_riscv_exts); i++) {
>                 if (__riscv_isa_extension_available(NULL, base_riscv_exts=
[i] - 'a'))
>                         /* Print only enabled the base ISA extensions */
> @@ -316,27 +319,21 @@ static int c_show(struct seq_file *m, void *v)
>         unsigned long cpu_id =3D (unsigned long)v - 1;
>         struct riscv_cpuinfo *ci =3D per_cpu_ptr(&riscv_cpuinfo, cpu_id);
>         struct device_node *node;
> -       const char *compat, *isa;
> +       const char *compat;
>
>         seq_printf(m, "processor\t: %lu\n", cpu_id);
>         seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
> +       print_isa(m);
> +               print_mmu(m);

Did the indent get wonky here or am I just seeing it wrong because gmail?
Otherwise:

Reviewed-by: Evan Green <evan@rivosinc.com>

>
>         if (acpi_disabled) {
>                 node =3D of_get_cpu_node(cpu_id, NULL);
> -               if (!of_property_read_string(node, "riscv,isa", &isa))
> -                       print_isa(m, isa);
>
> -               print_mmu(m);
>                 if (!of_property_read_string(node, "compatible", &compat)=
 &&
>                     strcmp(compat, "riscv"))
>                         seq_printf(m, "uarch\t\t: %s\n", compat);
>
>                 of_node_put(node);
> -       } else {
> -               if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
> -                       print_isa(m, isa);
> -
> -               print_mmu(m);
>         }
>
>         seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
> --
> 2.40.1
>