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Date:   Fri, 30 Jun 2023 11:21:53 +0300
From:   Pekka Paalanen <ppaalanen@gmail.com>
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc:     Jessica Zhang <quic_jesszhan@quicinc.com>,
        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
        Maxime Ripard <mripard@kernel.org>,
        Thomas Zimmermann <tzimmermann@suse.de>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
        Marijn Suijten <marijn.suijten@somainline.org>,
        quic_abhinavk@quicinc.com, contact@emersion.fr,
        laurent.pinchart@ideasonboard.com, sebastian.wick@redhat.com,
        ville.syrjala@linux.intel.com, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        freedreno@lists.freedesktop.org,
        wayland-devel@lists.freedesktop.org
Subject: Re: [PATCH RFC v4 6/7] drm/msm/dpu: Allow NULL FBs in atomic commit
Message-ID: <20230630112153.5da36b6a@eldfell>
In-Reply-To: <cca48c01-b84a-dff6-57ae-356971edacf3@linaro.org>
References: <20230404-solid-fill-v4-0-f4ec0caa742d@quicinc.com>
        <20230404-solid-fill-v4-6-f4ec0caa742d@quicinc.com>
        <cca48c01-b84a-dff6-57ae-356971edacf3@linaro.org>
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On Fri, 30 Jun 2023 03:52:37 +0300
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:

> On 30/06/2023 03:25, Jessica Zhang wrote:
> > Since solid fill planes allow for a NULL framebuffer in a valid commit,
> > add NULL framebuffer checks to atomic commit calls within DPU.
> >=20
> > Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> > ---
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  9 ++++++-
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 45 +++++++++++++++++++---=
---------
> >   2 files changed, 36 insertions(+), 18 deletions(-)
> >=20
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm=
/msm/disp/dpu1/dpu_crtc.c
> > index 1edf2b6b0a26..d1b37d2cc202 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -451,6 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_=
crtc *crtc,
> >   	struct drm_plane_state *state;
> >   	struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(crtc->state);
> >   	struct dpu_plane_state *pstate =3D NULL;
> > +	const struct msm_format *fmt;
> >   	struct dpu_format *format;
> >   	struct dpu_hw_ctl *ctl =3D mixer->lm_ctl;
> >  =20
> > @@ -470,7 +471,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm=
_crtc *crtc,
> >   		pstate =3D to_dpu_plane_state(state);
> >   		fb =3D state->fb;
> >  =20
> > -		format =3D to_dpu_format(msm_framebuffer_format(pstate->base.fb));
> > +		if (state->pixel_source =3D=3D DRM_PLANE_PIXEL_SOURCE_FB && fb)
> > +			fmt =3D msm_framebuffer_format(pstate->base.fb);
> > +		else
> > +			fmt =3D dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base,
> > +					DRM_FORMAT_RGBA8888, 0); =20
>=20
> The DRM_FORMAT_RGBA8888 should be defined somewhere in patch 1 as format=
=20
> for the solid_fill, then that define can be used in this patch.

Isn't this just a driver-specific decision to convert a RGB323232
solid_fill to be presented as a RGBA8888?

Though, below there is ABGR8888 used for something... inconsistent?


Thanks,
pq

>=20
> > +
> > +		format =3D to_dpu_format(fmt);
> >  =20
> >   		if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable)
> >   			bg_alpha_enable =3D true;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/dr=
m/msm/disp/dpu1/dpu_plane.c
> > index 5f0984ce62b1..4476722f03bb 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -837,8 +837,10 @@ static int dpu_plane_atomic_check(struct drm_plane=
 *plane,
> >  =20
> >   	pipe_cfg->dst_rect =3D new_plane_state->dst;
> >  =20
> > -	fb_rect.x2 =3D new_plane_state->fb->width;
> > -	fb_rect.y2 =3D new_plane_state->fb->height;
> > +	if (new_plane_state->pixel_source =3D=3D DRM_PLANE_PIXEL_SOURCE_FB &&=
 new_plane_state->fb) {
> > +		fb_rect.x2 =3D new_plane_state->fb->width;
> > +		fb_rect.y2 =3D new_plane_state->fb->height;
> > +	}
> >  =20
> >   	/* Ensure fb size is supported */
> >   	if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH ||
> > @@ -848,10 +850,13 @@ static int dpu_plane_atomic_check(struct drm_plan=
e *plane,
> >   		return -E2BIG;
> >   	}
> >  =20
> > -	fmt =3D to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
> > -
> >   	max_linewidth =3D pdpu->catalog->caps->max_linewidth;
> >  =20
> > +	if (drm_plane_solid_fill_enabled(new_plane_state))
> > +		fmt =3D dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
> > +	else
> > +		fmt =3D to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
> > +
> >   	if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
> >   		/*
> >   		 * In parallel multirect case only the half of the usual width
> > @@ -1082,21 +1087,32 @@ static void dpu_plane_sspp_atomic_update(struct=
 drm_plane *plane)
> >   	struct drm_crtc *crtc =3D state->crtc;
> >   	struct drm_framebuffer *fb =3D state->fb;
> >   	bool is_rt_pipe;
> > -	const struct dpu_format *fmt =3D
> > -		to_dpu_format(msm_framebuffer_format(fb));
> > +	const struct dpu_format *fmt;
> >   	struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg;
> >   	struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg;
> >   	struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base);
> >   	struct msm_gem_address_space *aspace =3D kms->base.aspace;
> >   	struct dpu_hw_fmt_layout layout;
> >   	bool layout_valid =3D false;
> > -	int ret;
> >  =20
> > -	ret =3D dpu_format_populate_layout(aspace, fb, &layout);
> > -	if (ret)
> > -		DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > -	else
> > -		layout_valid =3D true;
> > +	if (state->pixel_source =3D=3D DRM_PLANE_PIXEL_SOURCE_FB && fb) {
> > +		int ret;
> > +
> > +		fmt =3D to_dpu_format(msm_framebuffer_format(fb));
> > +
> > +		ret =3D dpu_format_populate_layout(aspace, fb, &layout);
> > +		if (ret)
> > +			DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > +		else
> > +			layout_valid =3D true;
> > +
> > +		DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT=
_FMT
> > +				", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
> > +				crtc->base.id, DRM_RECT_ARG(&state->dst),
> > +				(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
> > +	} else {
> > +		fmt =3D dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
> > +	}
> >  =20
> >   	pstate->pending =3D true;
> >  =20
> > @@ -1104,11 +1120,6 @@ static void dpu_plane_sspp_atomic_update(struct =
drm_plane *plane)
> >   	pstate->needs_qos_remap |=3D (is_rt_pipe !=3D pdpu->is_rt_pipe);
> >   	pdpu->is_rt_pipe =3D is_rt_pipe;
> >  =20
> > -	DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_=
FMT
> > -			", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
> > -			crtc->base.id, DRM_RECT_ARG(&state->dst),
> > -			(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
> > -
> >   	dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
> >   				   drm_mode_vrefresh(&crtc->mode),
> >   				   layout_valid ? &layout : NULL);
> >  =20
>=20


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