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From:   Prabhakar <prabhakar.csengg@gmail.com>
To:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-gpio@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [RFC PATCH 0/4] Add missing pins for RZ/Five SoC
Date:   Fri, 30 Jun 2023 13:04:29 +0100
Message-Id: <20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Geert,

This patch series intends to incorporate the absent port pins P19 to P28,
which are exclusively available on the RZ/Five SoC.

I am submitting this series as an RFC (Request for Comments) as the port
pins P19 to P28 cannot be utilized as GPIO but can be utilized as
multiplexed pins. Additionally, certain attributes such as setting the
ISEL would necessitate a device tree property to indicate ISEL. Therefore,
before proceeding with the addition of comprehensive support, I would
appreciate some input on whether an alternative approach could be considered.

Cheers,
Prabhakar

Lad Prabhakar (4):
  pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK()
    macro
  pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in
    rzg2l_gpio_request()
  pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
  riscv: dts: renesas: r9a07g043f: Update gpio-ranges property

 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi |   4 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c     | 263 +++++++++++++-------
 2 files changed, 176 insertions(+), 91 deletions(-)

-- 
2.34.1