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[2a01:cb05:86f5:6700:e8b4:437a:6bf7:1039]) by smtp.gmail.com with ESMTPSA id f1-20020a5d5681000000b0030647449730sm18606092wrv.74.2023.06.30.07.29.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jun 2023 07:29:06 -0700 (PDT) Message-ID: <69bcc286-f28f-0a41-8d39-0f1124f69ca8@broadcom.com> Date: Fri, 30 Jun 2023 16:29:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] irq-bcm6345-l1: do not assume a fixed block to cpu mapping To: Jonas Gorski , Florian Fainelli , Broadcom internal kernel review list , Thomas Gleixner , Marc Zyngier , Simon Arlott Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230629072620.62527-1-jonas.gorski@gmail.com> From: Florian Fainelli In-Reply-To: <20230629072620.62527-1-jonas.gorski@gmail.com> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000b8adbf05ff59a357" X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --000000000000b8adbf05ff59a357 Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/29/2023 8:26 AM, Jonas Gorski wrote: > The irq to block mapping is fixed, and interrupts from the first block > will always be routed to the first parent IRQ. But the parent interrupts > themselves can be routed to any available CPU. > > This is used by the bootloader to map the first parent interrupt to the > boot CPU, regardless wether the boot CPU is the first one or the second > one. > > When booting from the second CPU, the assumption that the first block's > IRQ is mapped to the first CPU breaks, and the system hangs because > interrupts do not get routed correctly. > > Fix this by passing the appropriate bcm6434_l1_cpu to the interrupt > handler instead of the chip itself, so the handler always has the right > block. > > Fixes: c7c42ec2baa1 ("irqchips/bmips: Add bcm6345-l1 interrupt controller") > Signed-off-by: Jonas Gorski Reviewed-by: Florian Fainelli -- Florian --000000000000b8adbf05ff59a357 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature 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