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Date:   Sat, 1 Jul 2023 16:04:15 +0800
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Subject: Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link
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To:     Andrew Lunn <andrew@lunn.ch>
CC:     <hkallweit1@gmail.com>, <davem@davemloft.net>,
        <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
        <linux@armlinux.org.uk>, <netdev@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <20230629034846.30600-1-quic_luoj@quicinc.com>
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 <924ebd8b-2e1f-4060-8c66-4f4746e88696@lunn.ch>
From:   Jie Luo <quic_luoj@quicinc.com>
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On 6/30/2023 9:21 PM, Andrew Lunn wrote:
>> SERDES device is the block converts data between serial data and parallel
>> interfaces in each direction, which is the SGMII interface in qca8081 PHY,
>> it's address is always the PHY address added by 1 in qca8081 PHY.
> 
> What other registers does this block have? What behaviour can be
> configured? Does it have any support for Clause 73? Is there an open
> datasheet for it?
> 
> 	    Andrew

Hi Andrew,
This block includes MII and MMD1 registers, which mainly configure the 
PLL clocks, reset and calibration of the interface sgmii, there is no 
related Clause 73 control register in this block.

Normally it is the hardware behavior, driver do not need to configure 
these registers, adding this interface fifo reset is for avoiding the 
packet block issue in some corner case.

it seems there is no open datasheet after searching the internet, but 
you can get the basic information of qca8081 from the following link.
https://www.qualcomm.com/products/internet-of-things/networking/wi-fi-networks/qca8081

Thanks,
Jie