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Date:   Sun, 2 Jul 2023 11:49:28 +0200
From:   Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>
To:     Michael Ellerman <mpe@ellerman.id.au>,
        Christophe Leroy <christophe.leroy@csgroup.eu>
Cc:     linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] powerpc: dts: turris1x.dts: Fix PCIe MEM size for pci2
 node
Message-ID: <20230702094928.hhuksy6aed5naz74@pali>
References: <20230505172818.18416-1-pali@kernel.org>
 <20230610073521.prpxivjcwtcfwl3u@pali>
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On Saturday 10 June 2023 09:35:21 Pali Rohár wrote:
> On Friday 05 May 2023 19:28:18 Pali Rohár wrote:
> > Freescale PCIe controllers on their PCIe Root Ports do not have any
> > mappable PCI BAR allocate from PCIe MEM.
> > 
> > Information about 1MB window on BAR0 of PCIe Root Port was misleading
> > because Freescale PCIe controllers have at BAR0 position different register
> > PEXCSRBAR, and kernel correctly skipts BAR0 for these Freescale PCIe Root
> > Ports.
> > 
> > So update comment about P2020 PCIe Root Port and decrease PCIe MEM size
> > required for PCIe controller (pci2 node) on which is on-board xHCI
> > controller.
> > 
> > lspci confirms that on P2020 PCIe Root Port is no PCI BAR and /proc/iomem
> > sees that only c0000000-c000ffff and c0010000-c0011fff ranges are used.
> > 
> > Fixes: 54c15ec3b738 ("powerpc: dts: Add DTS file for CZ.NIC Turris 1.x routers")
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> >  arch/powerpc/boot/dts/turris1x.dts | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/powerpc/boot/dts/turris1x.dts b/arch/powerpc/boot/dts/turris1x.dts
> > index 6612160c19d5..dff1ea074d9d 100644
> > --- a/arch/powerpc/boot/dts/turris1x.dts
> > +++ b/arch/powerpc/boot/dts/turris1x.dts
> > @@ -476,12 +476,12 @@
> >  		 * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
> >  		 * slot 1 (CN5), channels 2 and 3 to connector P600.
> >  		 *
> > -		 * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
> > +		 * P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
> >  		 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
> > -		 * So allocate 2MB of PCIe MEM for this PCIe bus.
> > +		 * So allocate 128kB of PCIe MEM for this PCIe bus.
> >  		 */
> >  		reg = <0 0xffe08000 0 0x1000>;
> > -		ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
> > +		ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00020000>, /* MEM */
> >  			 <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
> >  
> >  		pcie@0 {
> > -- 
> > 2.20.1
> > 
> 
> PING?

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