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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4657.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80a3dd08-d2b0-4de1-a9f5-08db7bc23d46 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2023 12:37:18.4444 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sYxsVzJgtF3aR9uS3FXMLuCua+815Q/tjvXirD5qgtak9TeulrplJ/ztthbgR/Ekie8sec84A69Aiqw5n+5RP7mAEvIEd/JqqoAfZavjE7Y= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB4873 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From: Jiri Pirko >Sent: Thursday, June 29, 2023 8:14 AM > >Wed, Jun 21, 2023 at 02:29:59PM CEST, jiri@resnulli.us wrote: >>Mon, Jun 19, 2023 at 10:34:12PM CEST, arkadiusz.kubalewski@intel.com >wrote: >>>>From: Jiri Pirko >>>>Sent: Saturday, June 10, 2023 6:37 PM >>>> >>>>Fri, Jun 09, 2023 at 02:18:51PM CEST, arkadiusz.kubalewski@intel.com >>>>wrote: >>>> >>>>[...] >>>> >>>> >>>>>+static int ice_dpll_mode_get(const struct dpll_device *dpll, void *pr= iv, >>>>>+ enum dpll_mode *mode, >>>>>+ struct netlink_ext_ack *extack) >>>>>+{ >>>>>+ *mode =3D DPLL_MODE_AUTOMATIC; >>>> >>>>I don't understand how the automatic mode could work with SyncE. The >>>>There is one pin exposed for one netdev. The SyncE daemon should select >>>>exacly one pin. How do you achieve that? >>>>Is is by setting DPLL_PIN_STATE_SELECTABLE on the pin-netdev you want t= o >>>>select and DPLL_PIN_STATE_DISCONNECTED on the rest? >>>> >>>> >>>>[...] >>> >>>AUTOMATIC mode autoselects highest priority valid signal. >>>As you have pointed out, for SyncE selection, the user must be able to >>>manually >>>select a pin state to enable recovery of signal from particular port. >>> >>>In "ice" case there are 2 pins for network PHY clock signal recovery, an= d >>>both >>>are parent pins (MUX-type). There are also 4 pins assigned to netdevs >>>(one per >>>port). Thus passing a signal from PHY to the pin is done through the MUX= - >>>pin, >>>by selecting proper state on pin-parent pair (where parent pins is highe= st >>>prio >>>pin on dpll). >> >>Could you show me some examples please? > >Arkadiusz, could you please reply to this? >Thanks! > Sure, sorry for the delays, let's try that. 'ice' use case: Enabling a PHY clock recovery for DPLL_MODE_AUTOMATIC dpll (ID#0) with PHY recovered clock signals (PIN_ID#13) being muxed using MUX-type pin (PIN_ID#= 2) 1. Set MUX-type pin to state selectable and highest priority on a dpll devi= ce (or make sure it is already configured): CMD_PIN_SET: PIN_ID 2 PIN_PARENT_DEVICE (nest) ID 0 PIN_STATE SELECTABLE PIN_PRIO 0 (assume all the other pins have prio >=3D1) 2. Set connected state on a pin-parent_pin tuple where parent is a pin from= #1 CMD_PIN_SET: PIN_ID 13 PIN_PARENT_PIN (nest) PIN_ID 2 PIN_STATE CONNECTED Thank you! Arkadiusz >> >> >>> >>>Thank you! >>>Arkadiusz