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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id ep7-20020a056512484700b004fbb1f70ceesm833417lfb.227.2023.07.03.06.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 06:31:13 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH 0/5] Add interconnects to QUPs on SM8250 Date: Mon, 03 Jul 2023 15:31:09 +0200 Message-Id: <20230703-topic-8250_qup_icc-v1-0-fea39aa07525@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJ3NomQC/x2N0QqDMAwAf0XyvEBtp5X9yhCpMZsBqV2rMhD/f WGPd3DcCYWzcIFHdULmQ4qsUaG+VUBziG9GmZTBGuuMNw63NQlhZxszfPY0CBG2tW+74O7kmUD DMRTGMYdIs6ZxXxaVKfNLvv/Ts7+uH6A3bfx5AAAA To: Andy Gross , Bjorn Andersson , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Andi Shyti Cc: Marijn Suijten , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1688391072; l=1274; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=P/b9sUtVGW1aCLv/5W9/Do7IS4MZ5AYwLEHs4cWI4Yo=; b=FeyN/5yDiFSyKCkhToHlIcdNwZzpYCsAzae8/E3MTmMzSSgehX8sZSykvbqgM4E5OR2o/LBXV pAWX9VvkUzICzoebYDjNNIbkASbiD70Z2u/I6lHttwRFt3eIaxT4Pcp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't provide a qup-core path. Adjust the bindings and drivers as necessary, and then describe the icc paths in the device tree. This makes it possible for interconnect sync_state succeed so long as you don't use UFS. Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path dt-bindings: serial: geni-qcom: Allow no qup-core icc path dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path soc: qcom: geni-se: Allow any combination of icc paths arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 27 ++-- .../bindings/serial/qcom,serial-geni-qcom.yaml | 26 ++-- .../bindings/spi/qcom,spi-geni-qcom.yaml | 15 ++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++ drivers/soc/qcom/qcom-geni-se.c | 9 +- 5 files changed, 204 insertions(+), 23 deletions(-) --- base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335 change-id: 20230703-topic-8250_qup_icc-61768a34c7ec Best regards, -- Konrad Dybcio