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Date:   Mon, 03 Jul 2023 21:49:37 +0800
From:   Li Chen <me@linux.beauty>
To:     "Achal Verma" <a-verma1@ti.com>
Cc:     "Vignesh Raghavendra" <vigneshr@ti.com>,
        "Tom Joseph" <tjoseph@cadence.com>,
        "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
        "Krzysztof Wilczy_ski" <kw@linux.com>,
        "Rob Herring" <robh@kernel.org>,
        "Bjorn Helgaas" <bhelgaas@google.com>,
        "linux-omap" <linux-omap@vger.kernel.org>,
        "linux-pci" <linux-pci@vger.kernel.org>,
        "linux-arm-kernel" <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel" <linux-kernel@vger.kernel.org>
Message-ID: <1891c041807.fea67a55448140.3454059194195387266@linux.beauty>
In-Reply-To: <20230703112914.68806-1-a-verma1@ti.com>
References: <20230703112914.68806-1-a-verma1@ti.com>
Subject: Re: [PATCH] PCI: j721e: Fix delay before PERST# deassert
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Hi Achal,
 ---- On Mon, 03 Jul 2023 19:29:14 +0800  Achal Verma  wrote --- 
 > As per the PCIe Card Electromechanical specification REV. 3.0, PERST#
 > signal should be de-asserted after minimum 100ms from the time power-rails
 > become stable. Current delay of 100us is observed to be not enough on some
 > custom platform implemented using TI's K3 SOCs.
 > 
 > So, to ensure 100ms delay to give sufficient time for power-rails and
 > refclk to become stable, change delay from 100us to 100ms.

What problems could arise if the delay is too small? Would some endpoints not be able to detect it?

Regards,
Li