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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Mon, 3 Jul 2023 22:10:21 +0100
Message-ID: <CA+V-a8tkZ8vbMPqReQ+CixQgHZWBXxzmNdjv1EL9skgaf+Mmvw@mail.gmail.com>
Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
 RZG2L_GPIO_PORT_PACK() macro
To:     Biju Das <biju.das.jz@bp.renesas.com>
Cc:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Biju,

On Mon, Jul 3, 2023 at 3:13=E2=80=AFPM Biju Das <biju.das.jz@bp.renesas.com=
> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, July 3, 2023 1:43 PM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> > Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Mon, Jul 3, 2023 at 12:42=E2=80=AFPM Biju Das <biju.das.jz@bp.renesa=
s.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Friday, June 30, 2023 1:05 PM
> > > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > > <magnus.damm@gmail.com>
> > > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > > RZG2L_GPIO_PORT_PACK() macro
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Currently we assume all the port pins are sequential ie always PX_0
> > > > to PX_n (n=3D1..7) exist, but on RZ/Five SoC we have additional pin=
s
> > > > P19_1 to
> > > > P28_5 which have holes in them, for example only one pin on port19
> > > > is available and that is P19_1 and not P19_0.
> > > >
> > > > So to handle such cases include pinmap for each port which would
> > > > indicate the pin availability on each port. With this we also get
> > > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > > pins
> > > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > > >
> > > > While at it, update rzg2l_validate_gpio_pin() to use the port pinma=
p
> > > > to validate the gpio pin.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > >  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > > ++++++++++++------------
> > > >  1 file changed, 86 insertions(+), 81 deletions(-)
> > > >
> > > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > index 9511d920565e..a0c2e585e765 100644
> > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > @@ -67,10 +67,12 @@
> > > >                                        PIN_CFG_FILCLKSEL)
> > > >
> > > >  /*
> > > > - * n indicates number of pins in the port, a is the register index
> > > > - * and f is pin configuration capabilities supported.
> > > > + * m indicates the bitmap of supported pins, n indicates number
> > > > + * of pins in the port, a is the register index and f is pin
> > > > + * configuration capabilities supported.
> > > >   */
> > > > -#define RZG2L_GPIO_PORT_PACK(n, a, f)        (((n) << 28) | ((a) <=
<
> > 20) |
> > > > (f))
> > > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f)     ((UL(m) << 32) |
> > (UL(n) << 28)
> > > > | ((a) << 20) | (f))
> > >
> > > I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
> > > ((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
> > >
> > > #define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify
> > rzg2l_gpio_configs.
> > >
> > Good point, but this would work if port pins didn't have any holes.
> > For example on RZ/Five port P19 we have P19_1 pin only and P19_0 is not
> > available (and similarly for port P25 we have P25_1).
>
> Maybe introduce a helper macro to address this case.
>
> #define RZG2L_GPIO_PORT_PACK_WITH_HOLES(m, n, a, f) for these 2 cases
>
> and use RZG2L_GPIO_PORT_PACK(n, a, f) for the one without holes.
>
Agreed will do.

Cheers,
Prabhakar