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From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Tue, 4 Jul 2023 14:23:34 +0800
Message-ID: <CAGXv+5E+1hVvCza_=vNse_ZNQNC4WSmrCF2zpqyUEgU5tR6Y6g@mail.gmail.com>
Subject: Re: [PATCH v4 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>, nfraprado@collabora.com
Cc:     =?UTF-8?Q?Bernhard_Rosenkr=C3=A4nzer?= <bero@baylibre.com>,
        daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org,
        rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org,
        ye.xingchen@zte.com.cn, p.zabel@pengutronix.de,
        linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
        james.lo@mediatek.com, rex-bc.chen@mediatek.com,
        abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com
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On Wed, May 31, 2023 at 4:07=E2=80=AFPM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 30/05/23 21:51, Bernhard Rosenkr=C3=A4nzer ha scritto:
> > From: Balsam CHIHI <bchihi@baylibre.com>
> >
> > Add LVTS Driver support for MT8192.
> >
> > Co-developed-by : N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
> > Signed-off-by: N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
> > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> > Reviewed-by: N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
> > Signed-off-by: Bernhard Rosenkr=C3=A4nzer <bero@baylibre.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> >   drivers/thermal/mediatek/lvts_thermal.c | 95 ++++++++++++++++++++++++=
+
> >   1 file changed, 95 insertions(+)
> >
> > diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/=
mediatek/lvts_thermal.c
> > index 5ea8a9d569ea6..d5e5214784ece 100644
> > --- a/drivers/thermal/mediatek/lvts_thermal.c
> > +++ b/drivers/thermal/mediatek/lvts_thermal.c
> > @@ -80,6 +80,7 @@
> >   #define LVTS_MSR_FILTERED_MODE              1
> >
> >   #define LVTS_HW_SHUTDOWN_MT8195             105000
> > +#define LVTS_HW_SHUTDOWN_MT8192              105000
> >
> >   static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT;
> >   static int coeff_b =3D LVTS_COEFF_B;
> > @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_a=
p_data_ctrl[] =3D {
> >       }
> >   };
> >
> > +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] =3D {
> > +     {
> > +             .cal_offset =3D { 0x04, 0x08 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_MCU_BIG_CPU0 },
> > +                     { .dt_id =3D MT8192_MCU_BIG_CPU1 }
> > +             },
> > +             .num_lvts_sensor =3D 2,
> > +             .offset =3D 0x0,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +             .mode =3D LVTS_MSR_FILTERED_MODE,
> > +     },
> > +     {
> > +             .cal_offset =3D { 0x0c, 0x10 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_MCU_BIG_CPU2 },
> > +                     { .dt_id =3D MT8192_MCU_BIG_CPU3 }
> > +             },
> > +             .num_lvts_sensor =3D 2,
> > +             .offset =3D 0x100,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +             .mode =3D LVTS_MSR_FILTERED_MODE,
> > +     },
> > +     {
> > +             .cal_offset =3D { 0x14, 0x18, 0x1c, 0x20 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_MCU_LITTLE_CPU0 },
> > +                     { .dt_id =3D MT8192_MCU_LITTLE_CPU1 },
> > +                     { .dt_id =3D MT8192_MCU_LITTLE_CPU2 },
> > +                     { .dt_id =3D MT8192_MCU_LITTLE_CPU3 }
> > +             },
> > +             .num_lvts_sensor =3D 4,
> > +             .offset =3D 0x200,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +             .mode =3D LVTS_MSR_FILTERED_MODE,
> > +     }
> > +};
> > +
> > +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] =3D {
> > +             {
> > +             .cal_offset =3D { 0x24, 0x28 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_AP_VPU0 },
> > +                     { .dt_id =3D MT8192_AP_VPU1 }
> > +             },
> > +             .num_lvts_sensor =3D 2,
> > +             .offset =3D 0x0,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +     },
> > +     {
> > +             .cal_offset =3D { 0x2c, 0x30 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_AP_GPU0 },
> > +                     { .dt_id =3D MT8192_AP_GPU1 }
> > +             },
> > +             .num_lvts_sensor =3D 2,
> > +             .offset =3D 0x100,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
>
> I'm unable to get readings for the GPU sensors, didn't really check
> the others; `cat (xxxx)` gives a resource not available error, is that
> the same for you?!

That could be related to the filtered mode stuff from Nicolas?

> Regards,
> Angelo
>
> > +     },
> > +     {
> > +             .cal_offset =3D { 0x34, 0x38 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_AP_INFRA },
> > +                     { .dt_id =3D MT8192_AP_CAM },
> > +             },
> > +             .num_lvts_sensor =3D 2,
> > +             .offset =3D 0x200,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +     },
> > +     {
> > +             .cal_offset =3D { 0x3c, 0x40, 0x44 },
> > +             .lvts_sensor =3D {
> > +                     { .dt_id =3D MT8192_AP_MD0 },
> > +                     { .dt_id =3D MT8192_AP_MD1 },
> > +                     { .dt_id =3D MT8192_AP_MD2 }
> > +             },
> > +             .num_lvts_sensor =3D 3,
> > +             .offset =3D 0x300,
> > +             .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192,
> > +     }
> > +};
> > +
> >   static const struct lvts_data mt8195_lvts_mcu_data =3D {
> >       .lvts_ctrl      =3D mt8195_lvts_mcu_data_ctrl,
> >       .num_lvts_ctrl  =3D ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
> > @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_dat=
a =3D {
> >       .num_lvts_ctrl  =3D ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
> >   };
> >
> > +static const struct lvts_data mt8192_lvts_mcu_data =3D {
> > +     .lvts_ctrl      =3D mt8192_lvts_mcu_data_ctrl,
> > +     .num_lvts_ctrl  =3D ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
> > +};
> > +
> > +static const struct lvts_data mt8192_lvts_ap_data =3D {
> > +     .lvts_ctrl      =3D mt8192_lvts_ap_data_ctrl,
> > +     .num_lvts_ctrl  =3D ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
> > +};
> > +
> >   static const struct of_device_id lvts_of_match[] =3D {
> >       { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_l=
vts_mcu_data },
> >       { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lv=
ts_ap_data },
> > +     { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_l=
vts_mcu_data },
> > +     { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lv=
ts_ap_data },
> >       {},
> >   };
> >   MODULE_DEVICE_TABLE(of, lvts_of_match);
>
>