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From:   Andy Chiu <andy.chiu@sifive.com>
Date:   Wed, 5 Jul 2023 11:50:50 +0800
Message-ID: <CABgGipVO35+CZUioxn2jFD8mFjVup84GRJXGQQ8wx4urjc0Y+Q@mail.gmail.com>
Subject: Re: [PATCH v4] riscv: Discard vector state on syscalls
To:     =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org,
        =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
        linux-kernel@vger.kernel.org, linux@rivosinc.com,
        Palmer Dabbelt <palmer@rivosinc.com>,
        =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= <remi@remlab.net>,
        Darius Rad <darius@bluespec.com>,
        Conor Dooley <conor.dooley@microchip.com>
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On Thu, Jun 29, 2023 at 10:22=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel <bjorn@kerne=
l.org> wrote:
>
> From: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>
>
> The RISC-V vector specification states:
>   Executing a system call causes all caller-saved vector registers
>   (v0-v31, vl, vtype) and vstart to become unspecified.
>
> The vector registers are set to all 1s, vill is set (invalid), and the
> vector status is set to Dirty.
>
> That way we can prevent userspace from accidentally relying on the
> stated save.
>
> R=C3=A9mi pointed out [1] that writing to the registers might be
> superfluous, and setting vill is sufficient.
>
> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.reml=
ab.net/ # [1]
> Suggested-by: Darius Rad <darius@bluespec.com>
> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
> Suggested-by: R=C3=A9mi Denis-Courmont <remi@remlab.net>
> Signed-off-by: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>

Thanks,
Reviewed-by: Andy Chiu <andy.chiu@sifive.com>