Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 6 Jul 2023 16:45:53 +0530
From:   Manivannan Sadhasivam <mani@kernel.org>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
Cc:     Mrinmay Sarkar <quic_msarkar@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, quic_shazhuss@quicinc.com,
        quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com,
        quic_nayiluri@quicinc.com,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Vinod Koul <vkoul@kernel.org>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org
Subject: Re: [PATCH v1 5/6] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1
 nodes
Message-ID: <20230706111553.GB4808@thinkpad>
References: <1688545032-17748-1-git-send-email-quic_msarkar@quicinc.com>
 <1688545032-17748-6-git-send-email-quic_msarkar@quicinc.com>
 <e31564e1-31cf-2cda-df6f-6210e6a1c1fc@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <e31564e1-31cf-2cda-df6f-6210e6a1c1fc@linaro.org>
Precedence: bulk

On Thu, Jul 06, 2023 at 12:01:37PM +0200, Konrad Dybcio wrote:
> On 5.07.2023 10:17, Mrinmay Sarkar wrote:
> > Add pcie dtsi nodes for two controllers found on sa8775p platform.
> > 
> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> > ---[...]
> 
> > +	pcie1_phy: phy@1c14000 {
> > +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> > +		reg = <0x0 0x1c14000 0x0 0x4000>;
> > +
> > +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > +			 <&gcc GCC_PCIE_CLKREF_EN>,
> > +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> > +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> > +
> > +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> > +						"pipe", "pipediv2";
> > +
> > +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> > +		assigned-clock-rates = <100000000>;
> > +
> > +		power-domains = <&gcc PCIE_1_GDSC>;
> Please check if it's the correct power domain. I've heard that the PCIe PHY
> may be hooked up to something else but have no way of confirming myself.
> 

Right, I missed it during my review. PHYs are powered by MX domain on all the
platforms I have seen so far, so this should be cross checked.

And someone should fix the existing dts.

- Mani

> Konrad
> > +
> > +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > +		reset-names = "phy";
> > +
> > +		#clock-cells = <0>;
> > +		clock-output-names = "pcie_1_pipe_clk";
> > +
> > +		#phy-cells = <0>;
> > +
> > +		status = "disabled";
> > +
> > +	};
> >  };

-- 
மணிவண்ணன் சதாசிவம்