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Date:   Thu, 6 Jul 2023 14:40:19 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Samuel Ortiz <sameo@rivosinc.com>
CC:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <linux-riscv@lists.infradead.org>,
        "Hongren (Zenithal) Zheng" <i@zenithal.me>, <linux@rivosinc.com>,
        Andrew Jones <ajones@ventanamicro.com>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>,
        Anup Patel <apatel@ventanamicro.com>,
        <linux-kernel@vger.kernel.org>, Guo Ren <guoren@kernel.org>,
        Atish Patra <atishp@rivosinc.com>,
        =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@rivosinc.com>,
        Evan Green <evan@rivosinc.com>,
        Jiatai He <jiatai2021@iscas.ac.cn>
Subject: Re: [PATCH v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT
Message-ID: <20230706-amused-entrench-3ce9cb6769ef@wendy>
References: <20230628131442.3022772-1-sameo@rivosinc.com>
 <20230628131442.3022772-2-sameo@rivosinc.com>
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Hey,

On Wed, Jun 28, 2023 at 03:14:33PM +0200, Samuel Ortiz wrote:
> From: "Hongren (Zenithal) Zheng" <i@zenithal.me>
>=20
> Parse Zb/Zk related string from DT and output them to cpuinfo.
>=20
> It is worth noting that the Scalar Crypto extension defines "zk" as a
> shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also
> implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid
> "zk" extension name through a DT will enable all of the  Zbkb, Zbkc,
> Zbkx, Zkn, Zkr and Zkt extensions.
>=20
> Also, since there currently is no mechanism to merge all enabled
> extensions, the generated cpuinfo output could be relatively large.
> For example, setting the "riscv,isa" DT property to "rv64imafdc_zk_zks"
> will generate the following cpuinfo output:
> "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt".
>=20
> Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
> Signed-off-by: Samuel Ortiz <sameo@rivosinc.com>
> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
> ---
>  arch/riscv/include/asm/hwcap.h | 11 +++++++++++
>  arch/riscv/kernel/cpu.c        | 11 +++++++++++
>  arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++
>  3 files changed, 52 insertions(+)
>=20
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwca=
p.h
> index f041bfa7f6a0..b80ca6e77088 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -53,6 +53,17 @@
>  #define RISCV_ISA_EXT_ZICSR		40
>  #define RISCV_ISA_EXT_ZIFENCEI		41
>  #define RISCV_ISA_EXT_ZIHPM		42
> +#define RISCV_ISA_EXT_ZBC		43
> +#define RISCV_ISA_EXT_ZBKB		44
> +#define RISCV_ISA_EXT_ZBKC		45
> +#define RISCV_ISA_EXT_ZBKX		46
> +#define RISCV_ISA_EXT_ZKND		47
> +#define RISCV_ISA_EXT_ZKNE		48
> +#define RISCV_ISA_EXT_ZKNH		49
> +#define RISCV_ISA_EXT_ZKR		50
> +#define RISCV_ISA_EXT_ZKSED		51
> +#define RISCV_ISA_EXT_ZKSH		52
> +#define RISCV_ISA_EXT_ZKT		53

Getting mighty close to running out of space in a u64 :)

I'd personally rather get my changes to this extensions stuff merged
before adding more extensions, but I am clearly biased in terms of
saving my own work there, and it'd not really be "fair" to hold it up
on that basis alone.
However, since Palmer has now merged the "riscv,isa" deprecation [1],
adding parsing of new ISA extensions, now requires documenting them in
the extensions dt-binding. Can you please do that in v3?

Otherwise, this looks good to me:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

1 - https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/=
?h=3Dfor-next&id=3Daeb71e42caae2031ec849a858080d81462cacca9

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