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Date:   Thu, 6 Jul 2023 09:30:35 -0500
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Subject: Re: [PATCH v2 2/4] pinctrl: amd: Use amd_pinconf_set() for all config
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To:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc:     Natikar Basavaraj <Basavaraj.Natikar@amd.com>,
        S-k Shyam-sundar <Shyam-sundar.S-k@amd.com>,
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        Hans de Goede <hdegoede@redhat.com>,
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References: <20230705133005.577-1-mario.limonciello@amd.com>
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From:   "Limonciello, Mario" <mario.limonciello@amd.com>
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 =?utf-8?B?Wm1TT3UzUWZsMm9sSG1GZW5xSUZBVitVcGZSRUhiTS93U1BLUndOeTIxVDBF?=
 =?utf-8?B?RDVrODVDTjFxNi8wOWp5OTB5RGlTWlJIb2h5UXRXL1pUV0ErTC9yaVMvNWE4?=
 =?utf-8?B?UTV2QUk1SUxyVU1xVldodmwyZFNreXdnQXZRQ05XMEh3MysrcURrSWt6R1Uv?=
 =?utf-8?B?QzBDQmQrc0dTYTVYb3BMeStNOGZxanJma2hEL2N0WlhVZmpxbzBHbVJ5Qkcz?=
 =?utf-8?B?K05KUXpUYnJvbkcwOEt0dTkvd0xFM3A0a1VXbll6TnpaSTFDTnVNUS9PRUJX?=
 =?utf-8?B?L2RQQ0RxbWJHRFZoc0lGam9LamZZc3BiRFBWb0RPNFNOWXZ3bnFlZzY0R2pw?=
 =?utf-8?B?NW9PVE1EcGFJSWd4aHFHRm9CdEY4aWZ3enh6WEJXb1NLMno3ZmRUaDAxR2dH?=
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 =?utf-8?B?RDJma1F4Wm50Mk5JU3FXYTlKSUVobHA0R2RDWFFBbnJ2bUJ0RVdRSEZHckRZ?=
 =?utf-8?B?emkvamwrUXVBdU9xUXVjUkVRb2Zidkw0RVJacVo4eG9XdXNHM0FqdFIxRy82?=
 =?utf-8?B?SGRFSlpiZDVxN1BVMk5qMUxlcGFLa0JKNVpReGZtcG5sRmQ5Rm15aFZVQStQ?=
 =?utf-8?B?dVlHeHB6OUpIZmlLeFB4ZHIvK2k3SURHL0R3YXd4b08yUVQ4ZDBMaEYrTGJt?=
 =?utf-8?B?Z2NQRXYwZlEwUGduaHppTjVuR2daQWlwUk5LNjYwWHp0RGZzNnhiUy8wUDgr?=
 =?utf-8?B?QVhLS0pHb0JGNFNqM2V6Z3UwaFhjYlp6V2JGN3pjQ0FrY3VMdTU2ZFRJRDkz?=
 =?utf-8?B?M2Zpc3pMTER5N0trU2JhREtjdXhueE1DRGJpSGZyeFN6M1gxSEFiU1VmUjRQ?=
 =?utf-8?B?dzh0K2pMNGdaUTZNSHZFTFRGODhtZCtHaXBEdkh6QVRUNVhncWNtUUo0allS?=
 =?utf-8?B?U1lxbWtNQkZBcU1NaDZDN1QraDBuS3k4eW9xdTBGRlF5UkhhdXYxSjhSeWVa?=
 =?utf-8?B?UU9MTkxNRHA2elZiUVQvMEpVY3VxNEpMQVJubVgycnI4Z3VjZlJTVGQrSit2?=
 =?utf-8?B?M1ltSGNJb3pEMms3bkVxTjdzMVpaZGhSSnBOaW5pUk5yd2I2dGk3T1FoSVQ5?=
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On 7/6/2023 04:16, Andy Shevchenko wrote:
> On Wed, Jul 05, 2023 at 08:30:03AM -0500, Mario Limonciello wrote:
>> On ASUS TUF A16 it is reported that the ITE5570 ACPI device connected to
>> GPIO 7 is causing an interrupt storm.  This issue doesn't happen on
>> Windows.
>>
>> Comparing the GPIO register configuration between Windows and Linux
>> bit 20 has been configured as a pull up on Windows, but not on Linux.
>> Checking GPIO declaration from the firmware it is clear it *should* have
>> been a pull up on Linux as well.
>>
>> ```
>> GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000,
>> 	 "\\_SB.GPIO", 0x00, ResourceConsumer, ,)
>> {   // Pin list
>> 0x0007
>> }
>> ```
>>
>> On Linux amd_gpio_set_config() is currently only used for programming
>> the debounce. Actually the GPIO core calls it with all the arguments
>> that are supported by a GPIO, pinctrl-amd just responds `-ENOTSUPP`.
>>
>> To solve this issue expand amd_gpio_set_config() to support the other
>> arguments amd_pinconf_set() supports, namely `PIN_CONFIG_BIAS_PULL_DOWN`,
>> `PIN_CONFIG_BIAS_PULL_UP`, and `PIN_CONFIG_DRIVE_STRENGTH`.
> 
> ...
> 
>> @@ -782,7 +770,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
>>   }
>>   
>>   static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
>> -				unsigned long *configs, unsigned num_configs)
>> +			   unsigned long *configs, unsigned int num_configs)
> 
> Seems like a stray change.

Right; if necessary I'll pull this into it's own patch instead of 
s,unsigned,unsigned long, in this one.  It just seemed sensible while 
calling this function.

> 
>>   {
>>   	int i;
>>   	u32 arg;
> 
> Otherwise entire series looks good to me,
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 

Thanks!