Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 06 Jul 2023 12:45:15 -0700 (PDT)
Subject:     Re: [PATCH v2] RISC-V: Show accurate per-hart isa in /proc/cpuinfo
In-Reply-To: <CALs-Hssc6Uxf-6FKbye2n-CD0FWWE4xDmUWvN1NoKNFpn88SKg@mail.gmail.com>
CC:     Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com,
        aou@eecs.berkeley.edu, apatel@ventanamicro.com,
        heiko.stuebner@vrull.eu, Paul Walmsley <paul.walmsley@sifive.com>,
        sunilvl@ventanamicro.com, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     Evan Green <evan@rivosinc.com>
Message-ID: <mhng-ebe222a1-57eb-41cf-a541-38b4b5595ac0@palmer-ri-x1c9a>
Mime-Version: 1.0 (MHng)
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Precedence: bulk

On Thu, 06 Jul 2023 12:34:30 PDT (-0700), Evan Green wrote:
> On Thu, Jul 6, 2023 at 3:53 AM Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> On Thu, Jul 06, 2023 at 10:01:31AM +0200, Andrew Jones wrote:
>> > On Wed, Jul 05, 2023 at 10:29:31AM -0700, Evan Green wrote:
>> > > In /proc/cpuinfo, most of the information we show for each processor is
>> > > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
>> > > compatible, and the mmu size. But the ISA string gets filtered through a
>> > > lowest common denominator mask, so that if one CPU is missing an ISA
>> > > extension, no CPUs will show it.
>> > >
>> > > Now that we track the ISA extensions for each hart, let's report ISA
>> > > extension info accurately per-hart in /proc/cpuinfo. We cannot change
>> > > the "isa:" line, as usermode may be relying on that line to show only
>> > > the common set of extensions supported across all harts. Add a new "hart
>> > > isa" line instead, which reports the true set of extensions for that
>> > > hart. This matches what is returned in riscv_hwprobe() when querying a
>> > > given hart.
>> > >
>> > > Signed-off-by: Evan Green <evan@rivosinc.com>
>> > >
>> > > ---
>> > >
>> > > Changes in v2:
>> > >  - Added new "hart isa" line rather than altering behavior of existing
>> > >    "isa" line (Conor, Palmer)
>> > >
>> > >
>> > > I based this series on top of Conor's riscv-extensions-strings branch
>> > > from July 3rd, since otherwise this change gets hopelessly entangled
>> > > with that series.
>> > >
>> > > I was unsure if I could snuggle the new "hart isa" line in just below
>> > > "isa". Aesthetically it would be quite pleasing, but it runs the risk of
>> > > breaking brittle usermode parsers that are assuming a specific line
>> > > order. So I put it at the end.
>> >
>> > Actually, they're probably only aesthetically pleasing when they match. If
>> > there are differences, then I'd guess having them side by side, almost the
>> > same, but different, would make them even harder to look at then they
>> > already are. So I think I'll be happier with them separated by a few lines
>> > anyway.
>>
>> This list is eventually going to be so big that I don't think doing
>> by-eye anything is going to be useful, so aesthetics be damned.
>> That said, a parser that relies on the order of individual lines like
>> that might deserve to be broken ;)
>>
>> Anyway, change looks good to me:
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>
>> I was thinking the uabi doc might need an update - should we add to it
>> that "isa" means the common set & "hart isa"?
>
> I did do a little search for documentation to update, but failed to
> come up with any. Which doc are you thinking of?

Should be somewhere like Documentation/arch/riscv/uabi.rst