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References: <20230706095841.109315-1-angelogioacchino.delregno@collabora.com>
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From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Fri, 7 Jul 2023 13:06:16 +0800
Message-ID: <CAGXv+5HsScBVMOY4JcSNS_ZZdpLnNAYWUKohwmfQr6gJJv26CA@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: mediatek: mt8195: Fix PM suspend/resume with
 venc clocks
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     matthias.bgg@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        yong.wu@mediatek.com, tinghan.shen@mediatek.com,
        weiyi.lu@mediatek.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, kernel@collabora.com
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On Thu, Jul 6, 2023 at 5:59=E2=80=AFPM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Before suspending the LARBs we're making sure that any operation is
> done: this never happens because we are unexpectedly unclocking the
> LARB20 before executing the suspend handler for the MediaTek Smart
> Multimedia Interface (SMI) and the cause of this is incorrect clocks
> on this LARB.
>
> Fix this issue by changing the Local Arbiter 20 (used by the video
> encoder secondary core) apb clock to CLK_VENC_CORE1_VENC;
> furthermore, in order to make sure that both the PM resume and video
> encoder operation is stable, add the CLK_VENC(_CORE1)_LARB clock to
> the VENC (main core) and VENC_CORE1 power domains, as this IP cannot
> communicate with the rest of the system (the AP) without local
> arbiter clocks being operational.

Somehow I feel like this is papering over some dependency issue in Linux.

> Fixes: 3b5838d1d82e ("arm64: dts: mt8195: Add iommu and smi nodes")
> Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@coll=
abora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/d=
ts/mediatek/mt8195.dtsi
> index 95bd058d6083..5c670fce1e47 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -626,6 +626,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
>
>                                         power-domain@MT8195_POWER_DOMAIN_=
VENC_CORE1 {
>                                                 reg =3D <MT8195_POWER_DOM=
AIN_VENC_CORE1>;
> +                                               clocks =3D <&vencsys_core=
1 CLK_VENC_CORE1_LARB>;
> +                                               clock-names =3D "venc1-la=
rb";
>                                                 mediatek,infracfg =3D <&i=
nfracfg_ao>;
>                                                 #power-domain-cells =3D <=
0>;
>                                         };
> @@ -688,6 +690,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
>
>                                                 power-domain@MT8195_POWER=
_DOMAIN_VENC {
>                                                         reg =3D <MT8195_P=
OWER_DOMAIN_VENC>;
> +                                                       clocks =3D <&venc=
sys CLK_VENC_LARB>;
> +                                                       clock-names =3D "=
venc0-larb";
>                                                         mediatek,infracfg=
 =3D <&infracfg_ao>;
>                                                         #power-domain-cel=
ls =3D <0>;
>                                                 };
> @@ -3094,7 +3098,7 @@ larb20: larb@1b010000 {
>                         reg =3D <0 0x1b010000 0 0x1000>;
>                         mediatek,larb-id =3D <20>;
>                         mediatek,smi =3D <&smi_common_vpp>;
> -                       clocks =3D <&vencsys_core1 CLK_VENC_CORE1_LARB>,
> +                       clocks =3D <&vencsys_core1 CLK_VENC_CORE1_VENC>,
>                                  <&vencsys_core1 CLK_VENC_CORE1_GALS>,
>                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSY=
S_CORE1>;
>                         clock-names =3D "apb", "smi", "gals";
> --
> 2.40.1
>
>