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From:   Anup Patel <apatel@ventanamicro.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>
Cc:     Atish Patra <atishp@atishpatra.org>,
        Andrew Jones <ajones@ventanamicro.com>,
        Sunil V L <sunilvl@ventanamicro.com>,
        Conor Dooley <conor@kernel.org>,
        Anup Patel <anup@brainfault.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 0/2] Misc RISC-V timer driver improvements
Date:   Mon, 10 Jul 2023 18:49:00 +0530
Message-Id: <20230710131902.1459180-1-apatel@ventanamicro.com>
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This series does two improvements to the RISC-V timer driver:
1) Keep timer interrupt enable state in-sync with interrupt subsystem
2) Increase rating of clock event device when Sstc is available

These patches can also be found in the riscv_timer_imp_v1 branch at:
https://github.com/avpatel/linux.git

Anup Patel (2):
  clocksource: timer-riscv: Don't enable/disable timer interrupt
  clocksource: timer-riscv: Increase rating of clock_event_device for
    Sstc

 drivers/clocksource/timer-riscv.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

-- 
2.34.1