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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u12-20020aa7d88c000000b0051da02e98dasi2148409edq.242.2023.07.11.07.22.26; Tue, 11 Jul 2023 07:22:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233495AbjGKOQH (ORCPT + 99 others); Tue, 11 Jul 2023 10:16:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233358AbjGKOQC (ORCPT ); Tue, 11 Jul 2023 10:16:02 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B805410CA; Tue, 11 Jul 2023 07:15:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB2991FB; Tue, 11 Jul 2023 07:16:41 -0700 (PDT) Received: from [10.57.30.34] (unknown [10.57.30.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CD5193F740; Tue, 11 Jul 2023 07:15:56 -0700 (PDT) Message-ID: <6143e1cd-4db7-d980-a189-b9b06f99d7c4@arm.com> Date: Tue, 11 Jul 2023 15:15:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH 4/4] perf: Remove unused PERF_PMU_CAP_HETEROGENEOUS_CPUS capability Content-Language: en-US To: Anshuman Khandual Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Will Deacon , Kan Liang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com References: <20230710122138.1450930-1-james.clark@arm.com> <20230710122138.1450930-5-james.clark@arm.com> <96a3d12a-71d8-1779-28a3-316e1838292e@arm.com> From: James Clark In-Reply-To: <96a3d12a-71d8-1779-28a3-316e1838292e@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/07/2023 13:10, Anshuman Khandual wrote: > > > On 7/10/23 17:51, James Clark wrote: >> Since commit bd2756811766 ("perf: Rewrite core context handling") the >> relationship between perf_event_context and PMUs has changed so that >> the error scenario that PERF_PMU_CAP_HETEROGENEOUS_CPUS originally >> silenced no longer exists. >> >> Remove the capability to avoid confusion that it actually influences >> any perf core behavior. This change should be a no-op. >> >> Signed-off-by: James Clark >> --- >> include/linux/perf_event.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h >> index d5628a7b5eaa..3f4d941fd6c5 100644 >> --- a/include/linux/perf_event.h >> +++ b/include/linux/perf_event.h >> @@ -288,7 +288,7 @@ struct perf_event_pmu_context; >> #define PERF_PMU_CAP_EXTENDED_REGS 0x0008 >> #define PERF_PMU_CAP_EXCLUSIVE 0x0010 >> #define PERF_PMU_CAP_ITRACE 0x0020 >> -#define PERF_PMU_CAP_HETEROGENEOUS_CPUS 0x0040 >> +/* Unused 0x0040 */ > > Small nit, "Unused" marking might not be required here. > But then it would be very easy to miss that there is a free bit if I don't leave the comment. Is it really better without it? I could shift all the following ones down by one bit, but it would be a lot of work to make sure that nobody has hard coded some check for one of the bits instead of using the define somewhere. >> #define PERF_PMU_CAP_NO_EXCLUDE 0x0080 >> #define PERF_PMU_CAP_AUX_OUTPUT 0x0100 >> #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0200