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Received: from DM4PR12MB6280.namprd12.prod.outlook.com (2603:10b6:8:a2::11) by MW6PR12MB7086.namprd12.prod.outlook.com (2603:10b6:303:238::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6565.32; Tue, 11 Jul 2023 16:19:33 +0000 Received: from DM4PR12MB6280.namprd12.prod.outlook.com ([fe80::68b9:3f7d:ca38:31ba]) by DM4PR12MB6280.namprd12.prod.outlook.com ([fe80::68b9:3f7d:ca38:31ba%7]) with mapi id 15.20.6565.028; Tue, 11 Jul 2023 16:19:33 +0000 Message-ID: <783e135b-b167-132a-fcd8-0ffce52ec259@amd.com> Date: Tue, 11 Jul 2023 12:19:30 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] amd/display: only accept async flips for fast updates To: =?UTF-8?Q?Andr=c3=a9_Almeida?= , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: pierre-eric.pelloux-prayer@amd.com, =?UTF-8?B?J01hcmVrIE9sxaHDoWsn?= , michel.daenzer@mailbox.org, Simon Ser , kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com References: <20230621202459.979661-1-andrealmeid@igalia.com> <20230621202459.979661-2-andrealmeid@igalia.com> Content-Language: en-US From: Hamza Mahfooz In-Reply-To: <20230621202459.979661-2-andrealmeid@igalia.com> Content-Type: text/plain; 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Xorg expects async flips to fail if > unsupported, to be able to fall back to a blit. i915 already behaves > this way. > > This patch aligns amdgpu with uAPI expectations and returns a failure > when an async flip is not possible. > > Signed-off-by: Simon Ser > Reviewed-by: André Almeida > Reviewed-by: Alex Deucher > Signed-off-by: André Almeida Applied, thanks! > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 514f6785a020..1d9b84e5835f 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -8136,7 +8136,15 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, > * Only allow immediate flips for fast updates that don't > * change memory domain, FB pitch, DCC state, rotation or > * mirroring. > + * > + * dm_crtc_helper_atomic_check() only accepts async flips with > + * fast updates. > */ > + if (crtc->state->async_flip && > + acrtc_state->update_type != UPDATE_TYPE_FAST) > + drm_warn_once(state->dev, > + "[PLANE:%d:%s] async flip with non-fast update\n", > + plane->base.id, plane->name); > bundle->flip_addrs[planes_count].flip_immediate = > crtc->state->async_flip && > acrtc_state->update_type == UPDATE_TYPE_FAST && > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > index 440fc0869a34..30d4c6fd95f5 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > @@ -398,6 +398,18 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, > return -EINVAL; > } > > + /* > + * Only allow async flips for fast updates that don't change the FB > + * pitch, the DCC state, rotation, etc. > + */ > + if (crtc_state->async_flip && > + dm_crtc_state->update_type != UPDATE_TYPE_FAST) { > + drm_dbg_atomic(crtc->dev, > + "[CRTC:%d:%s] async flips are only supported for fast updates\n", > + crtc->base.id, crtc->name); > + return -EINVAL; > + } > + > /* In some use cases, like reset, no stream is attached */ > if (!dm_crtc_state->stream) > return 0; -- Hamza