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From:   =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont <remi@remlab.net>
To:     linux-riscv@lists.infradead.org
Cc:     linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 03/12] RISC-V: add helper function to read the vector VLEN
Date:   Tue, 11 Jul 2023 21:06:32 +0300
Message-ID: <5073588.8QdJVB83L8@basile.remlab.net>
Organization: Remlab
In-Reply-To: <20230711153743.1970625-4-heiko@sntech.de>
References: <20230711153743.1970625-1-heiko@sntech.de>
 <20230711153743.1970625-4-heiko@sntech.de>
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Le tiistaina 11. heinäkuuta 2023, 18.37.34 EEST Heiko Stuebner a écrit :
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> 
> VLEN describes the length of each vector register and some instructions
> need specific minimal VLENs to work correctly.
> 
> The vector code already includes a variable riscv_vsize that contains the
> value of "32 vector registers with vlenb length" that gets filled during
> boot. vlenb is the value contained in the CSR_VLENB register and
> the value represents "VLEN / 8".
> 
> So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
> users when they need to check the available VLEN.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
>  arch/riscv/include/asm/vector.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h
> b/arch/riscv/include/asm/vector.h index ac2c23045eec..88cf76a2316d 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -232,4 +232,15 @@ static inline bool
> riscv_v_vstate_ctrl_user_allowed(void) { return false; }
> 
>  #endif /* CONFIG_RISCV_ISA_V */
> 
> +/*
> + * Return the implementation's vlen value.
> + *
> + * riscv_vsize contains the value of "32 vector registers with vlenb
> length" + * so rebuild the vlen value in bits from it.
> + */
> +static inline int riscv_vector_vlen(void)
> +{
> +	return riscv_v_vsize / 32 * 8;
> +}

KVM already has a bespoke conversion to bytes (rather than bits). Factor code?

> +
>  #endif /* ! __ASM_RISCV_VECTOR_H */


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