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Tue, 11 Jul 2023 22:55:29 +0000 Received: from AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7920:7c26:e953:83ac]) by AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7920:7c26:e953:83ac%7]) with mapi id 15.20.6588.017; Tue, 11 Jul 2023 22:55:22 +0000 From: "Mirela Rabulea (OSS)" To: Ming Qian , "shawnguo@kernel.org" , "Mirela Rabulea (OSS)" CC: "robh+dt@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , dl-linux-imx , "linux-media@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] arm64: dts: imx8-ss-img: Assign slot for imx jpeg encoder/decoder Thread-Topic: [PATCH] arm64: dts: imx8-ss-img: Assign slot for imx jpeg encoder/decoder Thread-Index: AQHZlDIsg2W97I7GdUqCR1rxzYI316+1bSVg Date: Tue, 11 Jul 2023 22:55:22 +0000 Message-ID: References: <20230601023801.25229-1-ming.qian@nxp.com> In-Reply-To: <20230601023801.25229-1-ming.qian@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS4PR04MB9244.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 481a42d8-e222-484a-f109-08db8261e876 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2023 22:55:22.6283 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Ti08jTOQp3u6Cdk2geu6kyPArfszzYIE8kiDUQW1PtVhDrsK+X+xX3gyHTEQx9o04g1PGnkL1UgSX7CWLhy+qw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8335 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ming, > -----Original Message----- > From: Ming Qian > Sent: Thursday, June 1, 2023 5:38 AM > To: shawnguo@kernel.org; Mirela Rabulea (OSS) > Cc: robh+dt@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de; dl= - > linux-imx ; linux-media@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: [PATCH] arm64: dts: imx8-ss-img: Assign slot for imx jpeg > encoder/decoder >=20 > assign a single slot, As I mentioned for the first patch of this series, I don't think it's ok to= limit the driver to using just one slot, the slot which is hardcoded in th= e dts. I suggest to hold off this patch series until we have a more clear p= icture how we want to change it for imx9. Regards, Mirela > configure interrupt and power domain only for 1 slot, not for the all 4 s= lots. >=20 > Signed-off-by: Ming Qian > --- > .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 22 +++++-------------- > 1 file changed, 6 insertions(+), 16 deletions(-) >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi > b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi > index a90654155a88..176dcce24b64 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi > @@ -18,10 +18,7 @@ img_ipg_clk: clock-img-ipg { >=20 > jpegdec: jpegdec@58400000 { > reg =3D <0x58400000 0x00050000>; > - interrupts =3D , > - , > - , > - ; > + interrupts =3D ; > clocks =3D <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, > <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; > clock-names =3D "per", "ipg"; > @@ -29,18 +26,13 @@ jpegdec: jpegdec@58400000 { > <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; > assigned-clock-rates =3D <200000000>, <200000000>; > power-domains =3D <&pd IMX_SC_R_MJPEG_DEC_MP>, > - <&pd IMX_SC_R_MJPEG_DEC_S0>, > - <&pd IMX_SC_R_MJPEG_DEC_S1>, > - <&pd IMX_SC_R_MJPEG_DEC_S2>, > - <&pd IMX_SC_R_MJPEG_DEC_S3>; > + <&pd IMX_SC_R_MJPEG_DEC_S0>; > + slot =3D <0>; > }; >=20 > jpegenc: jpegenc@58450000 { > reg =3D <0x58450000 0x00050000>; > - interrupts =3D , > - , > - , > - ; > + interrupts =3D ; > clocks =3D <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, > <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; > clock-names =3D "per", "ipg"; > @@ -48,10 +40,8 @@ jpegenc: jpegenc@58450000 { > <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; > assigned-clock-rates =3D <200000000>, <200000000>; > power-domains =3D <&pd IMX_SC_R_MJPEG_ENC_MP>, > - <&pd IMX_SC_R_MJPEG_ENC_S0>, > - <&pd IMX_SC_R_MJPEG_ENC_S1>, > - <&pd IMX_SC_R_MJPEG_ENC_S2>, > - <&pd IMX_SC_R_MJPEG_ENC_S3>; > + <&pd IMX_SC_R_MJPEG_ENC_S0>; > + slot =3D <0>; > }; >=20 > img_jpeg_dec_lpcg: clock-controller@585d0000 { > -- > 2.38.1