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[2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id h26-20020a170906261a00b00992f8110a2bsm2526819ejc.150.2023.07.12.05.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 05:31:45 -0700 (PDT) Date: Wed, 12 Jul 2023 14:31:43 +0200 From: Thierry Reding To: Guiting Shen Cc: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , claudiu.beznea@microchip.com, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] pwm: atmel: Enable clk when pwm already enabled in bootloader Message-ID: References: <20230711200905.6464-1-aarongt.shen@gmail.com> <20230711203017.cdfe2nrjx7lt25tm@pengutronix.de> <90830c22-0437-591e-cee0-67b16214bc55@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="eFQATVRlcI61GrFj" Content-Disposition: inline In-Reply-To: <90830c22-0437-591e-cee0-67b16214bc55@gmail.com> User-Agent: Mutt/2.2.10 (2023-03-25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --eFQATVRlcI61GrFj Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jul 12, 2023 at 09:45:08AM +0800, Guiting Shen wrote: > On Wed, Jul 12, 2023 at 04:30:17AM GMT+8, Uwe Kleine-K=C3=B6nig wrote: > > Hello, > >=20 > > On Wed, Jul 12, 2023 at 04:09:05AM +0800, Guiting Shen wrote: > >> +static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pw= m) > >> +{ > >> + unsigned int i; > >> + int err; > >> + u32 sr; > >> + > >> + sr =3D atmel_pwm_readl(atmel_pwm, PWM_SR); > >> + if (!sr) > >> + return 0; > >> + > >> + for (i =3D 0; i < atmel_pwm->chip.npwm; i++) { > >> + if (!(sr & (1 << i))) > >> + continue; > >> + > >> + err =3D clk_enable(atmel_pwm->clk); > >> + if (err) { > >> + dev_err(atmel_pwm->chip.dev, > >> + "failed to enable clock: %pe\n", ERR_PTR(err)); > >=20 > > Here you leak possibly a few enables. While it's not likely that the > > (say) third enable goes wrong, it's also not that hard to handle?! >=20 > The driver used the enable_count member of struct clk_core to count the > PWM channels(4 channels). It will enable hardware clock only when one of > the PWM channels becomed on from all PWM channels off which maybe return > error. And in second/third/fourth times to clk_enable(), it just > increased the enable_count of struct clk_core which would never return > error. >=20 > It maybe confused at first time to view the code. > Do it need to add something like that: ? >=20 > for (i =3D 0; i < atmel_pwm->chip.npwm; i++) { > if (!(sr & (1 << i))) > continue; >=20 > err =3D clk_enable(atmel_pwm->clk); > if (err) { > dev_err(atmel_pwm->chip.dev, > "failed to enable clock: %pe\n", ERR_PTR(err)); >=20 > for (i =3D 0; i < cnt; i++) > clk_disable(atmel_pwm->clk); > return err; > } > cnt++; You can also achieve this by decrementing i back to zero, that way you avoid the additional variable and you get a more natural unwinding of what you did before. So something like: while (i--) clk_disable(atmel_pwm->clk); should do the same thing. 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