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Message-ID: <a3dba5d9-918f-159f-161c-444a63d4c5b3@quicinc.com>
Date:   Wed, 12 Jul 2023 18:29:19 +0530
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Subject: Re: [PATCH v2 3/5] arm64: dts: qcom: ipq5332: Add tsens node
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To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, <amitk@kernel.org>,
        <thara.gopinath@gmail.com>, <agross@kernel.org>,
        <andersson@kernel.org>, <konrad.dybcio@linaro.org>,
        <rafael@kernel.org>, <daniel.lezcano@linaro.org>,
        <rui.zhang@intel.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <linux-pm@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
CC:     <quic_varada@quicinc.com>
References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com>
 <20230712113539.4029941-4-quic_ipkumar@quicinc.com>
 <a95dd01a-943f-e2d4-777f-a139fbc25238@linaro.org>
 <61346e56-3877-37c0-0df5-2436f97064e7@quicinc.com>
 <538c3d99-a404-6847-dd04-f77a35aa6c77@linaro.org>
From:   Praveenkumar I <quic_ipkumar@quicinc.com>
In-Reply-To: <538c3d99-a404-6847-dd04-f77a35aa6c77@linaro.org>
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On 7/12/2023 6:23 PM, Dmitry Baryshkov wrote:
> On 12/07/2023 15:48, Praveenkumar I wrote:
>>
>> On 7/12/2023 5:54 PM, Dmitry Baryshkov wrote:
>>> On 12/07/2023 14:35, Praveenkumar I wrote:
>>>> IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense
>>>> node with nvmem cells for calibration data.
>>>>
>>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>>>> ---
>>>> [v2]:
>>>>     Included qfprom nodes only for available sensors and removed
>>>>     the offset suffix.
>>>>
>>>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 
>>>> +++++++++++++++++++++++++++
>>>>   1 file changed, 66 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi 
>>>> b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> index 8bfc2db44624..0eef77e36609 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> @@ -150,6 +150,46 @@ qfprom: efuse@a4000 {
>>>>               reg = <0x000a4000 0x721>;
>>>>               #address-cells = <1>;
>>>>               #size-cells = <1>;
>>>> +
>>>> +            tsens_mode: mode@3e1 {
>>>> +                reg = <0x3e1 0x1>;
>>>> +                bits = <0 3>;
>>>> +            };
>>>> +
>>>> +            tsens_base0: base0@3e1 {
>>>> +                reg = <0x3e1 0x2>;
>>>> +                bits = <3 10>;
>>>> +            };
>>>> +
>>>> +            tsens_base1: base1@3e2 {
>>>> +                reg = <0x3e2 0x2>;
>>>> +                bits = <5 10>;
>>>> +            };
>
> Please order device nodes according to the address. So mode/base 
> should come after sensors data.
Sure, will reorder based on the address.

-- 
Thanks,
Praveenkumar
>
>>>> +
>>>> +            s11: s11@3a5 {
>>>> +                reg = <0x3a5 0x1>;
>>>> +                bits = <4 4>;
>>>> +            };
>>>> +
>>>> +            s12: s12@3a6 {
>>>> +                reg = <0x3a6 0x1>;
>>>> +                bits = <0 4>;
>>>> +            };
>>>> +
>>>> +            s13: s13@3a6 {
>>>> +                reg = <0x3a6 0x1>;
>>>> +                bits = <4 4>;
>>>> +            };
>>>> +
>>>> +            s14: s14@3ad {
>>>> +                reg = <0x3ad 0x2>;
>>>> +                bits = <7 4>;
>>>> +            };
>>>> +
>>>> +            s15: s15@3ae {
>>>> +                reg = <0x3ae 0x1>;
>>>> +                bits = <3 4>;
>>>> +            };
>>>>           };
>>>>             rng: rng@e3000 {
>>>> @@ -159,6 +199,32 @@ rng: rng@e3000 {
>>>>               clock-names = "core";
>>>>           };
>>>>   +        tsens: thermal-sensor@4a9000 {
>>>> +            compatible = "qcom,ipq5332-tsens";
>>>> +            reg = <0x4a9000 0x1000>,
>>>> +                  <0x4a8000 0x1000>;
>>>> +            nvmem-cells = <&tsens_mode>,
>>>> +                      <&tsens_base0>,
>>>> +                      <&tsens_base1>,
>>>> +                      <&s11>,
>>>> +                      <&s12>,
>>>> +                      <&s13>,
>>>> +                      <&s14>,
>>>> +                      <&s15>;
>>>> +            nvmem-cell-names = "mode",
>>>> +                       "base0",
>>>> +                       "base1",
>>>> +                       "s11",
>>>> +                       "s12",
>>>> +                       "s13",
>>>> +                       "s14",
>>>> +                       "s15";
>>>
>>> Previously you had data for other sensors here. Are they not used at 
>>> all, not wired, have no known-good placement? I think it might be 
>>> better to declare all sensors here (and in the driver too) and then 
>>> consider enabling only a pile of them in the thermal-zone node.
>>
>> Remaining sensors are not used at all. It is not wired. Only above 
>> sensors are placed in SoC.
>
> Ack, thanks for the explanation. Then this is good.
>
>>
>> - Praveenkumar
>>
>>>
>>>> +            interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
>>>> +            interrupt-names = "combined";
>>>> +            #qcom,sensors = <5>;
>>>> +            #thermal-sensor-cells = <1>;
>>>> +        };
>>>> +
>>>>           tlmm: pinctrl@1000000 {
>>>>               compatible = "qcom,ipq5332-tlmm";
>>>>               reg = <0x01000000 0x300000>;
>>>
>