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Date:   Wed, 12 Jul 2023 18:01:36 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     xingyu.wu@starfivetech.com, linux-riscv@lists.infradead.org,
        devicetree@vger.kernel.org, mturquette@baylibre.com,
        sboyd@kernel.org, p.zabel@pengutronix.de, kernel@esmil.dk,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, hal.feng@starfivetech.com,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v7 0/9] Add STG/ISP/VOUT clock and reset drivers for
 StarFive JH7110
Message-ID: <20230712-unsold-impound-02608d701dfb@spud>
References: <20230712092007.31013-1-xingyu.wu@starfivetech.com>
 <mhng-d3795910-5414-4555-bf3d-75ebe769ed2b@palmer-ri-x1c9a>
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On Wed, Jul 12, 2023 at 09:50:37AM -0700, Palmer Dabbelt wrote:
> On Wed, 12 Jul 2023 02:19:58 PDT (-0700), xingyu.wu@starfivetech.com wrot=
e:
> > This patch serises are base on the basic JH7110 SYSCRG/AONCRG
> > drivers and add new partial clock drivers and reset supports
> > about System-Top-Group(STG), Image-Signal-Process(ISP)
> > and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
> > clocks and resets could be used by DMA, VIN and Display modules.

> Happy to take it through the RISC-V tree if folks want, but IMO it's
> probably better aimed at the clock/reset folks.  Either way I'd want to g=
ive
> them a chance to ack/review it, so I'm going to drop it from my list.
>=20
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

I had a look through it & I am generally happy with it - everything has
either an R-b from DT folk or Hal on the drivers.
I was going to propose the same thing as the PLL patchset - if Emil is
happy with it, then I intend sending Stephen a PR for the drivers &
bindings.

Thanks,
Conor.

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