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From:   Tudor Ambarus <tudor.ambarus@linaro.org>
To:     pratyush@kernel.org, miquel.raynal@bootlin.com, richard@nod.at,
        vigneshr@ti.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc:     Tudor Ambarus <tudor.ambarus@linaro.org>, git@amd.com,
        michael@walle.cc, linux-mtd@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        amitrkcian2002@gmail.com
Subject: Re: [PATCH v4 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR
Date:   Thu, 13 Jul 2023 05:55:34 +0300
Message-Id: <168921680625.27728.7198640017398565535.b4-ty@linaro.org>
In-Reply-To: <20230630142233.63585-1-amit.kumar-mahapatra@amd.com>
References: <20230630142233.63585-1-amit.kumar-mahapatra@amd.com>
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On Fri, 30 Jun 2023 19:52:31 +0530, Amit Kumar Mahapatra wrote:
> Setting the status register write disable (SRWD) bit in the status
> register (SR) with WP# signal of the flash not connected or wrongly tied to
> GND (that includes internal pull-downs), will configure the SR permanently
> as read-only. To avoid this a boolean type DT property "no-wp" is
> introduced. If this property is defined, the spi-nor doesn't set the SRWD
> bit in SR while performing flash protection operation.
> 
> [...]

Moved the of_property_read_bool() as suggested by Michael.
Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git,
spi-nor/next branch. Thanks!

[1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register
      https://git.kernel.org/mtd/c/cfc2928cb213
[2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected
      https://git.kernel.org/mtd/c/18d7d01a0a0e

Cheers,
-- 
Tudor Ambarus <tudor.ambarus@linaro.org>