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From:   "Tian, Kevin" <kevin.tian@intel.com>
To:     Jacob Pan <jacob.jun.pan@linux.intel.com>,
        LKML <linux-kernel@vger.kernel.org>,
        "iommu@lists.linux.dev" <iommu@lists.linux.dev>,
        Lu Baolu <baolu.lu@linux.intel.com>,
        Joerg Roedel <joro@8bytes.org>,
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        "Robin Murphy" <robin.murphy@arm.com>
CC:     Jason Gunthorpe <jgg@nvidia.com>, Will Deacon <will@kernel.org>,
        "Liu, Yi L" <yi.l.liu@intel.com>,
        "Yu, Fenghua" <fenghua.yu@intel.com>,
        "Luck, Tony" <tony.luck@intel.com>
Subject: RE: [PATCH v10 2/7] iommu: Move global PASID allocation from SVA to
 core
Thread-Topic: [PATCH v10 2/7] iommu: Move global PASID allocation from SVA to
 core
Thread-Index: AQHZtN391/lvNgjG5EiNtGDik6wH1K+3UQwA
Date:   Thu, 13 Jul 2023 07:42:01 +0000
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References: <20230712163355.3177511-1-jacob.jun.pan@linux.intel.com>
 <20230712163355.3177511-3-jacob.jun.pan@linux.intel.com>
In-Reply-To: <20230712163355.3177511-3-jacob.jun.pan@linux.intel.com>
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> From: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Sent: Thursday, July 13, 2023 12:34 AM
>=20
>  }
> +
> +ioasid_t iommu_alloc_global_pasid_dev(struct device *dev)
> +{
> +	int ret;
> +
> +	/* max_pasids =3D=3D 0 means that the device does not support PASID */
> +	if (!dev->iommu->max_pasids)
> +		return IOMMU_PASID_INVALID;
> +
> +	/*
> +	 * max_pasids is set up by vendor driver based on number of PASID
> bits
> +	 * supported but the IDA allocation is inclusive.
> +	 */
> +	ret =3D ida_alloc_range(&iommu_global_pasid_ida,
> IOMMU_FIRST_GLOBAL_PASID,
> +			      dev->iommu->max_pasids - 1, GFP_KERNEL);
> +	return ret < 0 ? IOMMU_PASID_INVALID : ret;
> +}
> +EXPORT_SYMBOL_GPL(iommu_alloc_global_pasid_dev);

nit. Just call it iommu_alloc_global_pasid.