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Date:   Thu, 13 Jul 2023 13:38:37 +0200
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Subject: Re: [PATCH 1/6] dt-bindings: thermal: tsens: Add nvmem cells for
 calibration data
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To:     Praveenkumar I <quic_ipkumar@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, konrad.dybcio@linaro.org, amitk@kernel.org,
        thara.gopinath@gmail.com, rafael@kernel.org,
        daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     quic_varada@quicinc.com
References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com>
 <20230710103735.1375847-2-quic_ipkumar@quicinc.com>
 <09e33a89-c060-69b1-b94f-b21c45d1d249@linaro.org>
 <59ea653e-c5da-71cb-eb85-1aa3c72e2089@quicinc.com>
 <37aa7ae8-206e-3a48-b90d-22d49e86c675@linaro.org>
 <1b050086-07c5-add6-6002-d7368d532566@quicinc.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <1b050086-07c5-add6-6002-d7368d532566@quicinc.com>
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Precedence: bulk

On 11/07/2023 16:13, Praveenkumar I wrote:
>>>>>              - const: calib
>>>>> @@ -205,6 +209,24 @@ properties:
>>>>>              - const: s9_p2_backup
>>>>>              - const: s10_p1_backup
>>>>>              - const: s10_p2_backup
>>>>> +      - items:
>>>>> +          - const: mode
>>>>> +          - const: base0
>>>>> +          - const: base1
>>>>> +          - const: s0_offset
>>>>> +          - const: s3_offset
>>>>> +          - const: s4_offset
>>>>> +          - const: s5_offset
>>>>> +          - const: s6_offset
>>>>> +          - const: s7_offset
>>>>> +          - const: s8_offset
>>>>> +          - const: s9_offset
>>>>> +          - const: s10_offset
>>>>> +          - const: s11_offset
>>>>> +          - const: s12_offset
>>>>> +          - const: s13_offset
>>>>> +          - const: s14_offset
>>>>> +          - const: s15_offset
>>>> Don't introduce new naming style. Existing uses s[0-9]+, without offset
>>>> suffix. Why this should be different?
>>> As I mentioned above, s[0-9]+_p1 / s[0-9]+p2 is for TSENS V1. TSENS V2
>>> QFPROM layout is different from the existing one.
>> I know, I did not write about p1/p2.
>>
>>> I would like to add mode, base0, base1 and 16 patterns
>>> '^s[0-15]+_offset$'. But DT binding check is failing in oneOf/ anyOf
>>> condintion.
>> This does not explain why you need different style - this "offset" suffix.
> In QFPROM, the BIT field names are s0_offset, s3_offset to s15_offset. 
> s1_offset and s2_offset not present in IPQ5332.
> Hence used the same "offset" suffix here. May I know in this case, which 
> nvmem-cells-names you are suggesting to use?

"Existing uses s[0-9]+"

so s[0-9]+

Best regards,
Krzysztof