Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760457AbXJXVlx (ORCPT ); Wed, 24 Oct 2007 17:41:53 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1757002AbXJXVlk (ORCPT ); Wed, 24 Oct 2007 17:41:40 -0400 Received: from mx1.redhat.com ([66.187.233.31]:46702 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756646AbXJXVlj (ORCPT ); Wed, 24 Oct 2007 17:41:39 -0400 Message-ID: <471FBC09.8050201@redhat.com> Date: Wed, 24 Oct 2007 17:41:29 -0400 From: Chuck Ebbert Organization: Red Hat User-Agent: Thunderbird 1.5.0.12 (X11/20070719) MIME-Version: 1.0 To: Mikhail Kshevetskiy CC: linux-kernel@vger.kernel.org, Thomas Gleixner Subject: Re: x86_64 and AMD with C1E References: <20071001101532.025d652f@localhost> <4718DDB7.7070707@redhat.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 900 Lines: 24 On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote: >>> >>> I fill something wrong here. >>> Is it possible to reduce the amount of timer interrupts? >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled? >>> >> How are you disabling C1E? >> >> > dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic > initialization code. I make it for test purpose only, so i do not produce a > patch. > Why does disabling C1E disable C1, C2 and C3? Thomas, in the case of the machines where C1E is disabled on CPU 0 but enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the vendor just forgot to disable CPU 1... - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/