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Date:   Thu, 13 Jul 2023 21:38:12 +0200
From:   Sebastian Reichel <sebastian.reichel@collabora.com>
To:     Jagan Teki <jagan@edgeble.ai>
Cc:     Heiko Stuebner <heiko@sntech.de>,
        linux-rockchip@lists.infradead.org,
        Peter Geis <pgwipeout@gmail.com>,
        Elaine Zhang <zhangqing@rock-chips.com>,
        Finley Xiao <finley.xiao@rock-chips.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Boris Brezillon <boris.brezillon@collabora.com>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, kernel@collabora.com,
        Vincent Legoll <vincent.legoll@gmail.com>
Subject: Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks
 ignore unused
Message-ID: <20230713193812.px7q4sdfdppuywsg@mercury.elektranox.org>
References: <20230403193250.108693-1-sebastian.reichel@collabora.com>
 <20230403193250.108693-2-sebastian.reichel@collabora.com>
 <CA+VMnFz4USPcXmQMyUB9n5EVmvQrJARDvnpO7iBrXZ8q2xcyAA@mail.gmail.com>
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Hello Jagan,

On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
> On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
> <sebastian.reichel@collabora.com> wrote:
> [...]
> > + * Recent Rockchip SoCs have a new hardware block called Native Interf=
ace
> > + * Unit (NIU), which gates clocks to devices behind them. These effect=
ively
> > + * need two parent clocks.
> > + *
> > + * Downstream enables the linked clock via runtime PM whenever the gat=
e is
> > + * enabled. This implementation uses separate clock nodes for each of =
the
> > + * linked gate clocks, which leaks parts of the clock tree into DT.
> > + *
> > + * The GATE_LINK macro instead takes the second parent via 'linkname',=
 but
> > + * ignores the information. Once the clock framework is ready to handl=
e it, the
> > + * information should be passed on here. But since these clocks are re=
quired to
> > + * access multiple relevant IP blocks, such as PCIe or USB, we mark al=
l linked
> > + * clocks critical until a better solution is available. This will was=
te some
> > + * power, but avoids leaking implementation details into DT or hanging=
 the
> > + * system.
> >   */
>=20
> Does it mean the clk-link topology in the downstream kernel can be
> reused the same as normal clock notation?

Yes.

> For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
> of routing to pclk_vo1_grf(done downstream)
>       vo1_grf: syscon@fd5a8000 {
>                compatible =3D "rockchip,rk3588-vo-grf", "syscon";
>                reg =3D <0x0 0xfd5a8000 0x0 0x100>;
>              clocks =3D <&cru HCLK_VO1>;

You need PCLK_VO1 (which is currently not exposed; I somehow missed
it).

>       };
>=20
> This seems breaking syscon for vo1_grf and observed a bus error
> while accessing regmap.=20

I investigated the issue you are seeing some weeks ago when my
co-workers started to work on HDMI RX and TX. You are probably
just missing this patch:

https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/comm=
it/ecc6415344957fa88356cec10f8b75a9da603a7b

> I remember in one of the RKDC discussion that the double parenting
> of these clocks is mandatory while accessing associated IP blocks.

Yes, it is necessary.

> Any thoughts?

The upstream workaround/hack is to have the second parent always
enabled. This obviously wastes power, but means that the hardware
description in the DT is correct. Once the clock framework supports
two parents the kernel can be updated without touching the DT,
which is considered ABI.

Greetings,

-- Sebastian

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