Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Frank Li <Frank.Li@nxp.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Peng Fan <peng.fan@nxp.com>, Chester Lin <clin@suse.com>,
        Li Yang <leoyang.li@nxp.com>, Zhou Peng <eagle.zhou@nxp.com>,
        Pierre Gondois <pierre.gondois@arm.com>,
        devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
        DEVICE TREE BINDINGS),
        linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX
        / MXC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list)
Cc:     imx@lists.linux.dev
Subject: [PATCH v2 1/3] arm64: dts: imx8qm: add cpu frequency table
Date:   Thu, 13 Jul 2023 16:49:29 -0400
Message-Id: <20230713204932.1591255-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jHyR9Gn/6i33shYkx0RtFjLlYSTeFxcNCzRBO12MDI1FBmi2L/YtlMoxnvYY?=
 =?us-ascii?Q?XkKIATyHvInXANly2lHk5gH5sf+NrFPkPMZSSFUyFu4QdKdLl9qpqr+qc6ck?=
 =?us-ascii?Q?Oie+uAz+4Ss40NAht/f+e243w8AWLCYYpae/AnwhEQPLispsbzz6Km8aASZ+?=
 =?us-ascii?Q?jPVs+lrSATO1sFYV1UQhZ6V0Z42aVuFIjlenBSd4fXeMIU5H2tIpK0KGBSV+?=
 =?us-ascii?Q?X3H4M6nJds98mN7fO3rM9DSMFdRYT4nb190QNYch/HibjbvKCn6BaCVyq4Pw?=
 =?us-ascii?Q?9hfZfqmdjtFMBSh/7z7zwvN4rCTYv33DqeEDnlvXo25pvcf1hh8UXiK2GR7S?=
 =?us-ascii?Q?2Gx4cDt04kIsSAzdB4qaELqv/5oiUpPLaAsI6F1W5T43XMNSEL8FuRwkfugp?=
 =?us-ascii?Q?iXZyvcVwajkG8E/MYONSl4EUDMQk8F7mrH8XheRM2nQFJUjLzH40zVKEOPlt?=
 =?us-ascii?Q?uWixNDuSpGBUp+GX5D8wta9fXKTRGslA7OQrrfl7zEJn7psNMe2HxJD230xD?=
 =?us-ascii?Q?JLwg6HnoUGGPb4IAylI8gFbBA7tridRllrkCpKJLpr7PTsDRN/wqNRYQUjM6?=
 =?us-ascii?Q?69DiWZqxmMqW3JZvffxcR0rWcFt59b3Q6m4ZYIRDsPSXOjN4yxKrXQRnaoVO?=
 =?us-ascii?Q?JrVLCGIjGwYiG1KibfkXnxEYceIlL0s7+jP7rHs5CwKclG+80NN0uvnGgzpn?=
 =?us-ascii?Q?5/7UYVsOCTsHHNRXXWhZKyTRv27biYqel4UnUf1PG6LqEAkxln84JwALeYsV?=
 =?us-ascii?Q?aujKEofLUH6GfK6tQtY3zOdSJO9m+4CvI/QMZHF7KeoxnTWFtvf6r0hZ7bRL?=
 =?us-ascii?Q?CgJLwhLifV04YYMi0aeE5c3XtTlMszkVt4AJEtOPeNMQ2tAgqH9dT8m3QZQ8?=
 =?us-ascii?Q?jCECuBVmteUMWlqmJg9qe0OIs3JJhz9OO9rejau3Zk25zrwqX7Gcs2ftq40j?=
 =?us-ascii?Q?2S5hJsgITt4eVEUgIkO0zFPQ3iCvdcDUjldv5rYYpEbz08m53P2Yc2VJmFrh?=
 =?us-ascii?Q?626gFTh2iDg+Z5qeH7BCdu2nBkB/2/hKFaWv0wf2sV452kMit+AQAqiFFgZm?=
 =?us-ascii?Q?UGla+g0vFh+mkADMHpU27ZYnJW05ETRV3NMUTDZCMEFqyWRaiWZE8UCkRUvG?=
 =?us-ascii?Q?vFUCFawW61HU8ImP31E7O39x5x61DKZSG032iBhJSqEIddEjnLNw+VAVXJN7?=
 =?us-ascii?Q?k1TR9ZXwQbE3d0gj/UbPaCVLt4eZCN1cwcCgI+U/uHHaJaFBQuBgRfH3AGtX?=
 =?us-ascii?Q?DikE555+gedb3IzH0uEuFg152PwicAz/kUur0RpUt8BUZWbzn+A8NucWhBoE?=
 =?us-ascii?Q?YOGnqUC4c9V8lZo+32nir+GSYkK1YGbcYx/EJJVJ5JPwN2N8JOhHwAYnxfbx?=
 =?us-ascii?Q?lcG2kqGCAN0YUb/10pby0Jw4wuwOSMl2O7bRtVzt9ESp2dpSvmT75hzdaCI5?=
 =?us-ascii?Q?oKONzwqGYPJZD7zhciCKbwueWITIY+0qGcouzPhd4KqlG0HgiDF7mZvXdUwf?=
 =?us-ascii?Q?6bthkXEK1c4u8rgZyVfEtvbhM36TgFCQrzCZk5fivMZFDh8LsomSFPADpJvX?=
 =?us-ascii?Q?diVk7SGtfTkerk+bs72hBgfR86aDJTJAYiCT+2wy?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 7ca19d71-c101-42b7-36e9-08db83e2b467
X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2023 20:49:51.7128
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: E/lbGCSpKI3xlkO2i0gbleV5+2PmNcevEToXD5A+0V/BOFvsluwMuO8Z1Lv7NxBJz0SpZPqh/Ge3ETrFOZNk5Q==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB9731
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add A53 and A72 opp_table.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v1 to v2
- pass make dtbs_check

 arch/arm64/boot/dts/freescale/imx8qm.dtsi | 72 +++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 9fff867709f0..effd84ebade1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -62,6 +62,7 @@ A53_0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x0>;
+			clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
@@ -70,12 +71,14 @@ A53_0: cpu@0 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
 		};
 
 		A53_1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x1>;
+			clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
@@ -84,12 +87,14 @@ A53_1: cpu@1 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
 		};
 
 		A53_2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x2>;
+			clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
@@ -98,12 +103,14 @@ A53_2: cpu@2 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
 		};
 
 		A53_3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x3>;
+			clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
@@ -112,12 +119,14 @@ A53_3: cpu@3 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
 		};
 
 		A72_0: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72";
 			reg = <0x0 0x100>;
+			clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			i-cache-size = <0xC000>;
 			i-cache-line-size = <64>;
@@ -126,14 +135,17 @@ A72_0: cpu@100 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&A72_L2>;
+			operating-points-v2 = <&a72_opp_table>;
 		};
 
 		A72_1: cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72";
 			reg = <0x0 0x101>;
+			clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
 			enable-method = "psci";
 			next-level-cache = <&A72_L2>;
+			operating-points-v2 = <&a72_opp_table>;
 		};
 
 		A53_L2: l2-cache0 {
@@ -155,6 +167,66 @@ A72_L2: l2-cache1 {
 		};
 	};
 
+	a53_opp_table: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-896000000 {
+			opp-hz = /bits/ 64 <896000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
+	a72_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1296000000 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1596000000 {
+			opp-hz = /bits/ 64 <1596000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
 	gic: interrupt-controller@51a00000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
-- 
2.34.1