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Jul 2023 01:02:08.4384 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VvL3LwkUaI9lwSnrkLRPtupK6ENLV7Z3/cCEFB0+b1LslIpsAeDbxPGN+DGRJHZDQd2914bc7V0c+74ayJmPKM+9kXKUu0aselbsIuzT774G9NsL2IEUHFc8u3SWS14R X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY3PR01MB6611 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v4: * "Support implementation specific filters" patch: - Added comment about filter and impdef registers and reference to the Coresight PMU specification to the commit message * "Add support for Ampere SoC PMU" patch: - Fixed the documentation and added more comments - Changed the incrementing PMU index number to idr_alloc() (Needs a impdef release hook patch to release unused index) - Fixed style in init_ops() to more reasonable - Moved bank parameter to config1 Changes since v3: * use_64b_counter_reg => has_atomic_dword (patch 1/4) * Removed the unnecessary hook for group validation (patch 3/4) * Added group config validation to ampere_cspmu_validate_event() (patch 4/4) * Rebased the patchset Changes since v2: * Changed to use supports_64bits_atomics() and replaced the split writes with lo_hi_writeq() * Added implementation specific group validation to patch 3 * Dropped shared interrupt patch * Removed unnecessary filter_enable parameter from ampere module * Added group validation to ampere module Changes since v1: * Rather than creating a completely new driver, implemented as a submodule of Arm CoreSight PMU driver * Fixed shared filter handling Ilkka Koskinen (4): perf: arm_cspmu: Split 64-bit write to 32-bit writes perf: arm_cspmu: Support implementation specific filters perf: arm_cspmu: Support implementation specific validation perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU .../admin-guide/perf/ampere_cspmu.rst | 29 +++ drivers/perf/arm_cspmu/Makefile | 2 +- drivers/perf/arm_cspmu/ampere_cspmu.c | 243 ++++++++++++++++++ drivers/perf/arm_cspmu/ampere_cspmu.h | 17 ++ drivers/perf/arm_cspmu/arm_cspmu.c | 29 ++- drivers/perf/arm_cspmu/arm_cspmu.h | 6 + 6 files changed, 321 insertions(+), 5 deletions(-) create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.h -- 2.40.1