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Message-ID: <0019f59c-236f-4db9-825d-51bb9d655542@quicinc.com>
Date:   Fri, 14 Jul 2023 10:49:00 +0530
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Subject: Re: [PATCH V3 6/6] clk: qcom: gcc-qdu1000: Update the RCGs ops
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        "Michael Turquette" <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC:     Bjorn Andersson <andersson@kernel.org>,
        Taniya Das <quic_tdas@quicinc.com>,
        Melody Olvera <quic_molvera@quicinc.com>,
        <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Jagadeesh Kona <quic_jkona@quicinc.com>,
        Satya Priya Kakitapalli <quic_skakitap@quicinc.com>,
        Ajit Pandey <quic_ajipan@quicinc.com>
References: <20230706105045.633076-1-quic_imrashai@quicinc.com>
 <20230706105045.633076-7-quic_imrashai@quicinc.com>
 <fa24eaa0-c363-0694-76be-c14eba6999a1@linaro.org>
Content-Language: en-US
From:   Imran Shaik <quic_imrashai@quicinc.com>
In-Reply-To: <fa24eaa0-c363-0694-76be-c14eba6999a1@linaro.org>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 8bit
Precedence: bulk


On 7/6/2023 7:46 PM, Dmitry Baryshkov wrote:
> On 06/07/2023 13:50, Imran Shaik wrote:
>> Update the SDCC clock RCG ops to floor_ops to avoid overclocking issues
> 
> Split, please.
> 

Sure, will split this patch in next series.

>> and remaining RCGs to shared_ops to park them at safe clock(XO) during
>> disable.
> 
> Why are you doing this, is there any issue? Previously we had only a 
> several clocks implemented this way, which were really shared with other 
> subsystems (this is the where name _shared_ops comes from).
> 

 From our clock hardware side, the expectation is to park the RCGs at XO 
for most of the clocks and the shared_ops is the closest implementation 
for the same. Hence updating the RCG ops to clk_rcg2_shared_ops.

Thanks,
Imran

>>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> Changes since v2:
>>   - None
>> Changes since v1:
>>   - Newly added
>>
>>   drivers/clk/qcom/gcc-qdu1000.c | 62 +++++++++++++++++-----------------
>>   1 file changed, 31 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-qdu1000.c 
>> b/drivers/clk/qcom/gcc-qdu1000.c
>> index 718c34dca6e8..de35cdc93732 100644
>> --- a/drivers/clk/qcom/gcc-qdu1000.c
>> +++ b/drivers/clk/qcom/gcc-qdu1000.c
>> @@ -475,7 +475,7 @@ static struct clk_rcg2 
>> gcc_aggre_noc_ecpri_dma_clk_src = {
>>           .name = "gcc_aggre_noc_ecpri_dma_clk_src",
>>           .parent_data = gcc_parent_data_4,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_4),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -495,7 +495,7 @@ static struct clk_rcg2 
>> gcc_aggre_noc_ecpri_gsi_clk_src = {
>>           .name = "gcc_aggre_noc_ecpri_gsi_clk_src",
>>           .parent_data = gcc_parent_data_5,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_5),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -514,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
>>           .name = "gcc_gp1_clk_src",
>>           .parent_data = gcc_parent_data_1,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
>>           .name = "gcc_gp2_clk_src",
>>           .parent_data = gcc_parent_data_1,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -542,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
>>           .name = "gcc_gp3_clk_src",
>>           .parent_data = gcc_parent_data_1,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -561,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>>           .name = "gcc_pcie_0_aux_clk_src",
>>           .parent_data = gcc_parent_data_3,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -581,7 +581,7 @@ static struct clk_rcg2 
>> gcc_pcie_0_phy_rchng_clk_src = {
>>           .name = "gcc_pcie_0_phy_rchng_clk_src",
>>           .parent_data = gcc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
>>           .name = "gcc_pdm2_clk_src",
>>           .parent_data = gcc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -622,7 +622,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s0_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s0_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>> @@ -638,7 +638,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s1_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s1_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
>> @@ -654,7 +654,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s2_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s2_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
>> @@ -670,7 +670,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s3_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s3_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
>> @@ -686,7 +686,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s4_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s4_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
>> @@ -707,7 +707,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s5_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s5_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
>> @@ -723,7 +723,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s6_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s6_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
>> @@ -739,7 +739,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap0_s7_clk_src_init = {
>>       .name = "gcc_qupv3_wrap0_s7_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
>> @@ -755,7 +755,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s0_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s0_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
>> @@ -771,7 +771,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s1_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s1_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
>> @@ -787,7 +787,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s2_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s2_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
>> @@ -803,7 +803,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s3_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s3_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
>> @@ -819,7 +819,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s4_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s4_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
>> @@ -835,7 +835,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s5_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s5_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
>> @@ -851,7 +851,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s6_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s6_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
>> @@ -867,7 +867,7 @@ static struct clk_init_data 
>> gcc_qupv3_wrap1_s7_clk_src_init = {
>>       .name = "gcc_qupv3_wrap1_s7_clk_src",
>>       .parent_data = gcc_parent_data_0,
>>       .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -    .ops = &clk_rcg2_ops,
>> +    .ops = &clk_rcg2_shared_ops,
>>   };
>>   static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
>> @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
>>           .name = "gcc_sdcc5_apps_clk_src",
>>           .parent_data = gcc_parent_data_8,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_8),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_floor_ops,
>>       },
>>   };
>> @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
>>           .name = "gcc_sdcc5_ice_core_clk_src",
>>           .parent_data = gcc_parent_data_2,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_floor_ops,
>>       },
>>   };
>> @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
>>           .name = "gcc_sm_bus_xo_clk_src",
>>           .parent_data = gcc_parent_data_2,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = {
>>           .name = "gcc_tsc_clk_src",
>>           .parent_data = gcc_parent_data_9,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -975,7 +975,7 @@ static struct clk_rcg2 
>> gcc_usb30_prim_master_clk_src = {
>>           .name = "gcc_usb30_prim_master_clk_src",
>>           .parent_data = gcc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -989,7 +989,7 @@ static struct clk_rcg2 
>> gcc_usb30_prim_mock_utmi_clk_src = {
>>           .name = "gcc_usb30_prim_mock_utmi_clk_src",
>>           .parent_data = gcc_parent_data_0,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>> @@ -1003,7 +1003,7 @@ static struct clk_rcg2 
>> gcc_usb3_prim_phy_aux_clk_src = {
>>           .name = "gcc_usb3_prim_phy_aux_clk_src",
>>           .parent_data = gcc_parent_data_3,
>>           .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> -        .ops = &clk_rcg2_ops,
>> +        .ops = &clk_rcg2_shared_ops,
>>       },
>>   };
>