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From:   "Chanho Park" <chanho61.park@samsung.com>
To:     "'Krzysztof Kozlowski'" <krzysztof.kozlowski@linaro.org>,
        "'Jaewon Kim'" <jaewon02.kim@samsung.com>,
        "'Rob Herring'" <robh+dt@kernel.org>,
        "'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@linaro.org>,
        "'Conor Dooley'" <conor+dt@kernel.org>,
        "'Alim Akhtar'" <alim.akhtar@samsung.com>
Cc:     <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-samsung-soc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
In-Reply-To: <3bc9c34a-ba55-61c5-87ea-80b369841873@linaro.org>
Subject: RE: [PATCH] arm64: dts: exynos: add pwm node for exynosautov9-sadk
Date:   Fri, 14 Jul 2023 14:59:28 +0900
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> > +			reg =3D <0x103f0000 0x100>;
> > +			samsung,pwm-outputs =3D <0>, <1>, <2>, <3>;
> > +			=23pwm-cells =3D <3>;
> > +			clocks =3D <&xtcxo>;
>=20
> This does not look like correct clock. Are you sure XTCXO goes to PWM?

Yes. XTXCO is the source clock of the pwm. Unlike any other exynos SoCs, th=
e clock is directly derived from the external OSC.
Thus, it cannot be controllable such as gating.

Best Regards,
Chanho Park