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References: <20230703124647.215952-1-alexghiti@rivosinc.com> <20230703124647.215952-6-alexghiti@rivosinc.com>
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From:   Atish Patra <atishp@atishpatra.org>
Date:   Fri, 14 Jul 2023 01:03:00 -0700
Message-ID: <CAOnJCULGBpwb1ATtg8jdteoy9KKE_=f2HktvqrmqzWY2KNvi=g@mail.gmail.com>
Subject: Re: [PATCH v4 05/10] riscv: Prepare for user-space perf event mmap support
To:     Alexandre Ghiti <alexghiti@rivosinc.com>
Cc:     Jonathan Corbet <corbet@lwn.net>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>,
        Ian Rogers <irogers@google.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <anup@brainfault.org>,
        Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>,
        Andrew Jones <ajones@ventanamicro.com>,
        linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org
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On Mon, Jul 3, 2023 at 5:51=E2=80=AFAM Alexandre Ghiti <alexghiti@rivosinc.=
com> wrote:
>
> Provide all the necessary bits in the generic riscv pmu driver to be
> able to mmap perf events in userspace: the heavy lifting lies in the
> driver backend, namely the legacy and sbi implementations.
>
> Note that arch_perf_update_userpage is almost a copy of arm64 code.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  drivers/perf/riscv_pmu.c       | 105 +++++++++++++++++++++++++++++++++
>  include/linux/perf/riscv_pmu.h |   4 ++
>  2 files changed, 109 insertions(+)
>
> diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
> index ebca5eab9c9b..432ad2e80ce3 100644
> --- a/drivers/perf/riscv_pmu.c
> +++ b/drivers/perf/riscv_pmu.c
> @@ -14,9 +14,73 @@
>  #include <linux/perf/riscv_pmu.h>
>  #include <linux/printk.h>
>  #include <linux/smp.h>
> +#include <linux/sched_clock.h>
>
>  #include <asm/sbi.h>
>
> +static bool riscv_perf_user_access(struct perf_event *event)
> +{
> +       return ((event->attr.type =3D=3D PERF_TYPE_HARDWARE) ||
> +               (event->attr.type =3D=3D PERF_TYPE_HW_CACHE) ||
> +               (event->attr.type =3D=3D PERF_TYPE_RAW)) &&
> +               !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
> +}
> +
> +void arch_perf_update_userpage(struct perf_event *event,
> +                              struct perf_event_mmap_page *userpg, u64 n=
ow)
> +{
> +       struct clock_read_data *rd;
> +       unsigned int seq;
> +       u64 ns;
> +
> +       userpg->cap_user_time =3D 0;
> +       userpg->cap_user_time_zero =3D 0;
> +       userpg->cap_user_time_short =3D 0;
> +       userpg->cap_user_rdpmc =3D riscv_perf_user_access(event);
> +
> +       userpg->pmc_width =3D 64;
> +
> +       do {
> +               rd =3D sched_clock_read_begin(&seq);
> +
> +               userpg->time_mult =3D rd->mult;
> +               userpg->time_shift =3D rd->shift;
> +               userpg->time_zero =3D rd->epoch_ns;
> +               userpg->time_cycles =3D rd->epoch_cyc;
> +               userpg->time_mask =3D rd->sched_clock_mask;
> +
> +               /*
> +                * Subtract the cycle base, such that software that
> +                * doesn't know about cap_user_time_short still 'works'
> +                * assuming no wraps.
> +                */
> +               ns =3D mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift=
);
> +               userpg->time_zero -=3D ns;
> +
> +       } while (sched_clock_read_retry(seq));
> +
> +       userpg->time_offset =3D userpg->time_zero - now;
> +
> +       /*
> +        * time_shift is not expected to be greater than 31 due to
> +        * the original published conversion algorithm shifting a
> +        * 32-bit value (now specifies a 64-bit value) - refer
> +        * perf_event_mmap_page documentation in perf_event.h.
> +        */
> +       if (userpg->time_shift =3D=3D 32) {
> +               userpg->time_shift =3D 31;
> +               userpg->time_mult >>=3D 1;
> +       }
> +
> +       /*
> +        * Internal timekeeping for enabled/running/stopped times
> +        * is always computed with the sched_clock.
> +        */
> +       userpg->cap_user_time =3D 1;
> +       userpg->cap_user_time_zero =3D 1;
> +       userpg->cap_user_time_short =3D 1;
> +}
> +
>  static unsigned long csr_read_num(int csr_num)
>  {
>  #define switchcase_csr_read(__csr_num, __val)          {\
> @@ -171,6 +235,8 @@ int riscv_pmu_event_set_period(struct perf_event *eve=
nt)
>
>         local64_set(&hwc->prev_count, (u64)-left);
>
> +       perf_event_update_userpage(event);
> +
>         return overflow;
>  }
>
> @@ -267,6 +333,9 @@ static int riscv_pmu_event_init(struct perf_event *ev=
ent)
>         hwc->idx =3D -1;
>         hwc->event_base =3D mapped_event;
>
> +       if (rvpmu->event_init)
> +               rvpmu->event_init(event);
> +
>         if (!is_sampling_event(event)) {
>                 /*
>                  * For non-sampling runs, limit the sample_period to half
> @@ -283,6 +352,39 @@ static int riscv_pmu_event_init(struct perf_event *e=
vent)
>         return 0;
>  }
>
> +static int riscv_pmu_event_idx(struct perf_event *event)
> +{
> +       struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu);
> +
> +       if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
> +               return 0;
> +
> +       if (rvpmu->csr_index)
> +               return rvpmu->csr_index(event) + 1;
> +
> +       return 0;
> +}
> +
> +static void riscv_pmu_event_mapped(struct perf_event *event, struct mm_s=
truct *mm)
> +{
> +       struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu);
> +
> +       if (rvpmu->event_mapped) {
> +               rvpmu->event_mapped(event, mm);
> +               perf_event_update_userpage(event);
> +       }
> +}
> +
> +static void riscv_pmu_event_unmapped(struct perf_event *event, struct mm=
_struct *mm)
> +{
> +       struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu);
> +
> +       if (rvpmu->event_unmapped) {
> +               rvpmu->event_unmapped(event, mm);
> +               perf_event_update_userpage(event);
> +       }
> +}
> +
>  struct riscv_pmu *riscv_pmu_alloc(void)
>  {
>         struct riscv_pmu *pmu;
> @@ -307,6 +409,9 @@ struct riscv_pmu *riscv_pmu_alloc(void)
>         }
>         pmu->pmu =3D (struct pmu) {
>                 .event_init     =3D riscv_pmu_event_init,
> +               .event_mapped   =3D riscv_pmu_event_mapped,
> +               .event_unmapped =3D riscv_pmu_event_unmapped,
> +               .event_idx      =3D riscv_pmu_event_idx,
>                 .add            =3D riscv_pmu_add,
>                 .del            =3D riscv_pmu_del,
>                 .start          =3D riscv_pmu_start,
> diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pm=
u.h
> index 5deeea0be7cb..43282e22ebe1 100644
> --- a/include/linux/perf/riscv_pmu.h
> +++ b/include/linux/perf/riscv_pmu.h
> @@ -55,6 +55,10 @@ struct riscv_pmu {
>         void            (*ctr_start)(struct perf_event *event, u64 init_v=
al);
>         void            (*ctr_stop)(struct perf_event *event, unsigned lo=
ng flag);
>         int             (*event_map)(struct perf_event *event, u64 *confi=
g);
> +       void            (*event_init)(struct perf_event *event);
> +       void            (*event_mapped)(struct perf_event *event, struct =
mm_struct *mm);
> +       void            (*event_unmapped)(struct perf_event *event, struc=
t mm_struct *mm);
> +       uint8_t         (*csr_index)(struct perf_event *event);
>
>         struct cpu_hw_events    __percpu *hw_events;
>         struct hlist_node       node;
> --
> 2.39.2
>

Reviewed-by: Atish Patra <atishp@rivosinc.com>

--=20
Regards,
Atish