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Date:   Fri, 14 Jul 2023 11:47:05 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Prathamesh Shete <pshete@nvidia.com>
Cc:     linus.walleij@linaro.org, jonathanh@nvidia.com,
        linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] pinctrl: tegra: Add support to display pin function
Message-ID: <ZLEZmX0LzwCNvf5h@orome>
References: <ZK7BRXa9geC8SAGs@orome>
 <20230713082106.838-1-pshete@nvidia.com>
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On Thu, Jul 13, 2023 at 01:51:06PM +0530, Prathamesh Shete wrote:
> The current function for a given pin is not displayed via the debugfs.
> Add support to display the current function that is set for each pin.
>=20
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
>  drivers/pinctrl/tegra/pinctrl-tegra.c | 19 +++++++++++++++++--
>  drivers/pinctrl/tegra/pinctrl-tegra.h |  2 ++
>  2 files changed, 19 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegr=
a/pinctrl-tegra.c
> index 4547cf66d03b..4da8873942cf 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -96,6 +96,7 @@ static const struct cfg_param {
>  	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
>  	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
>  	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},
> +	{"nvidia,function",			TEGRA_PINCONF_PARAM_FUNCTION},
>  };
> =20
>  static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> @@ -470,6 +471,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
>  		*bit =3D g->drvtype_bit;
>  		*width =3D 2;
>  		break;
> +	case TEGRA_PINCONF_PARAM_FUNCTION:
> +		*bank =3D g->mux_bank;
> +		*reg =3D g->mux_reg;
> +		*bit =3D g->mux_bit;
> +		*width =3D 2;
> +		break;
>  	default:
>  		dev_err(pmx->dev, "Invalid config param %04x\n", param);
>  		return -ENOTSUPP;
> @@ -620,6 +627,7 @@ static void tegra_pinconf_group_dbg_show(struct pinct=
rl_dev *pctldev,
>  	s8 bank, bit, width;
>  	s32 reg;
>  	u32 val;
> +	u8 idx;

This declaration could be moved into the only conditional that uses this
variable...

> =20
>  	g =3D &pmx->soc->groups[group];
> =20
> @@ -633,8 +641,15 @@ static void tegra_pinconf_group_dbg_show(struct pinc=
trl_dev *pctldev,
>  		val >>=3D bit;
>  		val &=3D (1 << width) - 1;
> =20
> -		seq_printf(s, "\n\t%s=3D%u",
> -			   strip_prefix(cfg_params[i].property), val);
> +		if (cfg_params[i].param =3D=3D TEGRA_PINCONF_PARAM_FUNCTION) {
> +			idx =3D pmx->soc->groups[group].funcs[val];

=2E.. so that this would become:

			u8 idx =3D ...;

Either way:

Acked-by: Thierry Reding <treding@nvidia.com>

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